WP_Term Object
(
    [term_id] => 15564
    [name] => PLDA
    [slug] => plda
    [term_group] => 0
    [term_taxonomy_id] => 15564
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 3
    [filter] => raw
    [cat_ID] => 15564
    [category_count] => 3
    [category_description] => 
    [cat_name] => PLDA
    [category_nicename] => plda
    [category_parent] => 178
)
            
PLDA Logo
WP_Term Object
(
    [term_id] => 15564
    [name] => PLDA
    [slug] => plda
    [term_group] => 0
    [term_taxonomy_id] => 15564
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 3
    [filter] => raw
    [cat_ID] => 15564
    [category_count] => 3
    [category_description] => 
    [cat_name] => PLDA
    [category_nicename] => plda
    [category_parent] => 178
)

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
by Mike Gianfagna on 05-28-2020 at 10:00 am

A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay at the leading edge of these standards so support is available early in the design process.

A recent press release from PLDA illustrates the company’s commitment to emerging standards. Entitled PLDA Announce Complete Support for CXL™ and Gen-Z™ protocols, the announcement has a back-story worth mentioning.

First, let’s look at the CXL protocol. Compute Express Link (CXL) is a new high-speed interconnect specification that focuses on CPU-to-device and CPU-to-memory applications. The technology maintains memory coherency between the CPU memory space and memory on attached devices, which improves performance and lowers complexity and cost. The spec is being developed by an open industry standard group formed by some very prestigious companies.

Gen-Z is a new data-access technology that offers low-latency for data and devices through direct-attached, switched or fabric topologies. Gen-Z fabrics utilize memory-semantic communications to move data, which minimizes overhead.  Gen-Z is also developed by an industry consortium that has its own A-list members. Some of you may be wondering what memory-semantic communications is. The consortium posted this on Twitter to help: “What is memory semantic fabric? Communication at the speed of memory. A comm protocol that speaks the same language the CPU speaks”.

The goal of standards like CXL and Gen-Z is to enhance communication between compute and main memory to support more complex storage structures within and across systems. For further reading, this article sums it up as follows: “It will be hard to tell the difference between a system and a cluster … where there are memory servers, compute servers, and storage servers, all glued with a Gen-Z fabric into a very memory centric cluster.” Looking at the two standards, there is no Gen-Z without CXL. As these standards are deployed, Gen-Z will be bridged to CXL to extend CPU reach beyond the compute node, in composable data centers for rack/row/long-haul communication. Gen-Z expected to replace Infiniband in this scenario.

There’s one more important development to mention. On April 2, 2020, the CXL Consortium and the Gen-Z Consortium announced a memorandum of understanding. In an ecosystem that is characterized by highly competitive and secretive behavior, it is noteworthy that these two organizations decided to collaborate for the greater good. As stated in the announcement, “The MOU outlines the formation of common workgroups between both organizations to provide clear cooperation, defining bridging between the protocols while leveraging the strengths of both technologies.”

It is against this backdrop that the recent PLDA press release was made. Thanks to the clarifications provided by the MOU, PLDA is committed to support both protocols, with a focus on CXL IP first.

XpressLINK CXL is a parameterizable soft IP controller designed for both ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA’s silicon-proven XpressRICH Controller for PCIe 5.0 architectures. The IP includes:

  • Support for the CXL 2.0 specification
  • Implementation of the CXL.io, CXL.mem, and CXL.cache protocols
  • Support for all three defined CXL device types
  • Support for the PCI Express 5.0 Base Specification, Revision 1.0
  • Support for the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface widths

Regarding availability, PLDA’s current XpressLINK CXL roadmap extends from the second half of 2019 to the first half of 2021. This aligns well with the roadmap of processor vendors like Intel. PLDA is already engaged with early adopters for this technology.

“The announcement of the MoU between the CXL and GenZ Consortiums is a key event in the IP Market as it paves the way to the future architecture of high speed interfaces,” said Arnaud Schleich, CEO of PLDA. “As an historic actor in this Industry, it was logical for PLDA to expand its product line to include both protocols and we are proud to be committed to pushing this evolution to the next level.”

Gen-Z early silicon is not expected before the second half of 2022. As stated by Gen-Z Consortium Chairman Kurtis Bowman in April 2020: “… Gen-Z early adopters will be coming online in 2022 and it will be mainstream by 2023 to 2024….”). PLDA’s roadmap for Gen-Z IP begins in 2021, but the company already demonstrated a proof of concept of their Gen-Z at SuperComputing 2019.

Supporting two emerging, complex protocols at the leading edge is not easy.  PLDA appears to have done a great job here. For more information on this new standards-based IP, you can visit PLDA’s CXL IP webpage or PLDA’s Gen-Z IP webpage.


Comments

There are no comments yet.

You must register or log in to view/post comments.