For those who design advanced and complex SoCs, the term “off-the-shelf IP” can be elusive. While this approach works for a wide range of IP titles, the pressure for maximum performance or minimum power can lead to custom-tailoring requirements for the IP.
PLDA has seen these requirements for the class of complex, high-performance IP the company is known for, such as PCIe 5.0 or CXL. Often, PLDA customers will require very specific features and configurations which trigger an IP modification cycle. In spite of this, each customer is expecting the delivered product to be proven, robust and reliable, as though it had been used in many prior tapeouts. This is a daunting requirement, but it’s the price of admission into the high-end IP market.
PLDA has developed a thoughtful and rigorous approach to this challenge. They’ve even developed an ecosystem to support their efforts – more on that later. I had the opportunity to get an overview of the work going on in IP verification from Romain Tourneau, Marketing Manager at PLDA.
Romain started with an overview of the spec requirements from the customer that need to be understood and managed. These include:
- Functional requirements: behavior rules (this event is causing this consequence)
- Parametric requirements: performance, gate count, power consumption
- Structural/physical requirements: must be synthesizable, prone to metastability (CDC)
Aiming for a quality deliverable means requirements qualification to identify the “golden”, or most important items. Maximizing ways to verify these golden requirements then becomes the focus. This activity follows an implementation, debug and improvement process. There are many approaches to manage this process, including:
- The standard approach (single process start to finish)
- The incremental approach (following design changes incrementally)
- The “Sprint” approach (the project is split into small, incremental releases)
- The “Super-sprint” approach (same as Sprint, but accelerated timing)
PLDA uses the Super-sprint approach, which is summarized below:
While there are still many manual and time-consuming tasks to perform, the iterative nature of the Super-sprint method allows for efficient collaboration with the customer. It requires a deep verification discussion with the customer at project kickoff in order to fulfill these objectives:
- Understanding the customer’s process and tools
- Know the customer’s verification plan and IP usage and associated cost
- Explain PLDA process and tools
- Identify gaps in design criteria and address possible solutions
- Explain the advantages and importance of the customer starting IP verification early in their project since PLDA can provide a ready-to-use verification environment to perform this stand-alone verification earlier
To further solidify their commitment to robust verification, PLDA recently announced a Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect. The announcement details a comprehensive verification strategy that includes components from PLDA’s own verification process as well as tools from Aldec, Avery Design Systems and Mentor, a Siemens Business.
You typically don’t often see such a proactive and broad approach to IP verification – this is noteworthy. The release states:
“The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication. It is much more efficient to ensure a robust and high-quality initial verification process.” This is a very informed and evolved point of view in my opinion.
Dubbed the Robust Verification Toolset, it includes:
- Verification IPs covering standards compliance for PCIe, AMBA AXI, CXL, CCIX and Gen-Z
- Simulators that support mixed-language designs with UVM testbenches
- Synthesis and static verification tools from classic EDA providers, delivering verification of quality of RTL design and of CDC
To manage the data generated by the Robust Verification Toolset during both the verification and validation processes, PLDA has developed an interface named DANA.
This proprietary PLDA tool is used to deliver highly efficient supply chain management through a collection of automatic reports, flow automation and strict follow-up processes. Data from the complete toolset is automatically collected, analyzed, and reported. This reduces review cycles caused by data management and accelerates the decision-making process. A great gain of time for both projects leaders and verification engineers.
To learn more about PLDA’s verification solutions:
- Review the technical article from Mentor and PLDA: “PCIe simulation speed-up using Mentor QVIP with PLDA PCIe Controller for DMA application” at DAC 2020.
- Don’t miss the Aldec PCIe 5.0 Simulation/Verification demonstration in partnership with both PLDA and Avery at DAC 2020
- For more information about PLDA’s verification process, please visit plda.com
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