Mitigating AI Data Bottlenecks with PCIe 7.0

Mitigating AI Data Bottlenecks with PCIe 7.0
by Kalar Rajendiran on 08-05-2024 at 6:00 am

Mitigating AI Data Bottlenecks with PCIe 7.0 LinkedIn Event

During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More


PCIe 6.0, LPDDR5, HBM2E and HBM3 Speed Adapters to FPGA Prototyping Solutions

PCIe 6.0, LPDDR5, HBM2E and HBM3 Speed Adapters to FPGA Prototyping Solutions
by Kalar Rajendiran on 12-15-2021 at 6:00 am

Avery PCIe Speed Adapter IP at Work

We live in the age of big data. No matter how fast and complex modern SoCs are, it all comes down to how quickly data can get in and out that determines the system performance. And, there is a lot of data that today’s systems need to process. Naturally, system interfaces such as PCIe, DDR, HBM, etc., have been evolving rapidly too, to support… Read More


PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers

PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers
by Mike Gianfagna on 11-30-2020 at 10:00 am

PLDA Brings Flexible Support for Compute Express Link CXL to SoC and FPGA Designers

A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™.  The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More


Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5

Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5
by Mike Gianfagna on 09-09-2020 at 10:00 am

Design Integration of Complete On die Clock Subsystem for PCIe Gen 5

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC.  The talk covered here focuses on a complete on-die clock … Read More


PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem

PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem
by Mike Gianfagna on 07-21-2020 at 10:00 am

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For those who design advanced and complex SoCs, the term “off-the-shelf IP” can be elusive. While this approach works for a wide range of IP titles, the pressure for maximum performance or minimum power can lead to custom-tailoring requirements for the IP.

PLDA has seen these requirements for the class of complex, high-performance… Read More


Turbo-Charge Your Next PCIe SoC with PLDA Switch IP

Turbo-Charge Your Next PCIe SoC with PLDA Switch IP
by Mike Gianfagna on 03-12-2020 at 6:00 am

Integrated NVMe interfaces

SemiWiki has a new IP partner, PLDA and they bring a lot to the party.  Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous… Read More


PCIe 5.0 Jumps to the Fore in 2019

PCIe 5.0 Jumps to the Fore in 2019
by Tom Simon on 03-06-2019 at 12:00 pm

2019 will be a big year for PCIe. With the approval of version 0.9 of the Base Layer for PCIe 5.0, implementers have a solid foundation to begin working on designs. PCIe 4.0 was introduced in 2017, before that the previous PCIe 3.0 was introduced in 2010 – ages ago in this industry. In fact, 5.0 is so close on the heels of 4.0, many products… Read More