SemiWiki has a new IP partner, PLDA and they bring a lot to the party. Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous standards such as serial ATA. The last application has spawned a new standard that bundles SSDs with PCIe, creating non-volatile memory express (NVMe) drives.
With all that jargon out of the way, let’s explore how PLDA makes a difference in the NVMe market. One approach to system design with NVMe drives is to use discrete interfaces, as shown below.
While this approach reduces SoC design complexity, it has some significant drawbacks – lower performance and the ability to differentiate only in software are two. Here is where PLDA makes a difference.
Thanks to their embedded PCIe switch IP, the SoC can now handle all the interface tasks previously done by discrete parts. This means improved performance, an optimized bill-of-materials (BoM) and power profile, system design flexibility (e.g., host and/or flash controller implementation in one device) and future-proof capabilities thanks to PLDA’s support of the latest standards, up to PCIe 5.0.
Integrating the PCIe switch into the SoC opens up other opportunities for
further differentiation. For example, hardware-based accelerators can be added to the SoC for tasks such as encryption and compression, resulting in lower latency, power and a reduced BoM. Thanks to PLDA’s support for non-transparent bridges (NTB), multiple guest hosts can be added to the configuration as well. Host-to-host communication is supported by NTB, and guest host to device communication can be implemented with address translation.
Differentiation at the appliance level is also possible with a modular design to support low-cost to high-end applications through multiple instances of the same SoC/FPGA.
PLDA summarizes the key features of their IP for these applications as follows:
- Low latency switch (cut-through architecture)
- Support of PCIe 4.0 or 5.0 and SR-IOV
- RAS features includes ECRC, Parity, ECC, AER, Hot Plug
- Support for inline and/or embedded processing via pipelining and/or embedded endpoints
- Any port to any port high-speed communication including peer-to-peer between endpoint devices
- Ability to support different link width and speed on downstream ports
- Downstream Port Containment (DPC)
Keep an eye on SemiWiki for more information on PLDA’s flexible IP portfolio, you can also get the big picture regarding PLDA’s full line of products and support at the PLDA website.Share this post via: