Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.
After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief History of Synopsys DesignWare IP blog I did back in 2013. I also found the “Executive and Expert Access: Accelerating High-Performance Computing SoC Designs with Synopsys IP” webinar series and the DesignWare IP University (which I will be spending more time on in the coming days).
Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required functionality for your chip and deliver competitive products to market faster:
- The New Frontier of Die-to-Die Connectivity: What You Need to Know for Silicon Success
- Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals
- Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs
I just finished this on-demand webinar series. It’s easy to register and you get immediate access. The format is a 10 minute executive introduction, a 40 minute technical presentation, and a 10 minute Q&A, this is excellent content!
John Koeter is the Synopsys IP executive in the webinar series. John has been at Synopsys for more than 20 years and is one of the foremost semiconductor IP experts.
The Product Expert Speakers are:
Manmeet Walia brings over 18 years of experience in product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and an MBA from San Diego State University.
Graham Allan brings over 25 years of experience in the memory industry. Graham has spoken at numerous industry conferences and is a significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards. He currently holds 25 issued patents in the area of memory design.
Gary Ruggles brings over 25 years of experience in electronics and integrated circuit design. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing.
This webinar series is definitely worth your time.
The DesignWare IP University is organized into 7 topics:
- Interface IP
- Processor IP
- Foundation IP
- Security IP
- Artificial Intelligence
- Cloud Computing
Most of of these are trending topics on SemiWiki. Under each topic there are on-demand webinars, videos, event presentations, and white papers. This is an excellent resource that should be shared.
Learn about the latest interface protocols and standards, processor implementation techniques, and market trends in these educational white papers, webinars, and videos. Whether your chip design includes artificial intelligence capabilities, targets next-generation cars, or enables massive data in the cloud, the DesignWare IP University resources will help you create the SoC your market needs.
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.