WP_Term Object
(
    [term_id] => 28
    [name] => Dolphin Design
    [slug] => dolphin-design
    [term_group] => 0
    [term_taxonomy_id] => 28
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 10
    [filter] => raw
    [cat_ID] => 28
    [category_count] => 10
    [category_description] => 
    [cat_name] => Dolphin Design
    [category_nicename] => dolphin-design
    [category_parent] => 178
)
            
WP_Term Object
(
    [term_id] => 28
    [name] => Dolphin Design
    [slug] => dolphin-design
    [term_group] => 0
    [term_taxonomy_id] => 28
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 10
    [filter] => raw
    [cat_ID] => 28
    [category_count] => 10
    [category_description] => 
    [cat_name] => Dolphin Design
    [category_nicename] => dolphin-design
    [category_parent] => 178
)

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs
by Tom Simon on 05-29-2020 at 6:00 am

When it comes to extremely power sensitive applications such as IoT and edge devices, there is literally an arsenal of power saving techniques that could be used. The tricky part is figuring out which ones to use and how to use them for maximum benefit. This is coupled with the need to not hamper device performance or functionality. The trend is for increasing use of Ultra Low Power 32-bit microcontrollers (ULP MCUs) in SOCs for devices such as industrial instrumentation solutions, industrial controllers, connected home consoles, thermostats, temperature sensors, smart meters, smart grids, blood glucose meters, heart rate monitors, implantable devices, and IoT devices.

ULP SoC Demand

The range of possible power reduction techniques go from device and cell level to block and chip level, including mixed Vth cells, body biasing, thick oxides, clock gating, power gating, frequency scaling, always on domains, etc. Some of these techniques can be applied once during design and can be ‘forgotten’. Others need intelligence of their own to help manage them in conjunction with chip operation. Dolphin Design has recently published a white paper that does a good job of reviewing traditional and new power management techniques and discussing how they can and should be applied. The paper is titled “Breaking new energy efficiency records with advanced power management platform. “

Dolphin Design cites reports that show the ULP MCU market growing from $4.4B to $12.9B from 2019 to 2024. Many of these ULP MCUs will support analog mixed signal IoT devices that will have very complex operation modes and need to operate for weeks, months or years on a single batter or charge.

The white paper takes a look at various methods of power management, starting with off-chip PMICs, then progressing to on-chip Power Management Units (PMU) and programmable PMUs. Moving from a discrete PMIC to an on-chip power management approach reduces the BOM and permits tighter integration of power management functions. One drawback of on-chip software based power management is that the processor needs be ‘always-on’ which makes it a power sink, especially for chips that spend significant time in sleep modes. The alternative is to design FSM based logic that can provide most of the functions needed for power management, with reduced power consumption. Yet, FSM based PMUs are not as flexible

Dolphin Design describes their comprehensive power management solution Spider in their white paper. Their approach uses a power controller called MAESTRO, which is fully configurable IP that works like a state machine, but can but reprogrammed in the field if desired.

But there is a lot more to it. Dolphin Design have a comprehensive set of regulator IP that are extremely efficient at converting battery and supply voltages to on-chip logic levels. They are configurable as well, providing flexibility. Dolphin Design talks about their ultra-low leakage IP that are used for the always-on blocks. These include LDOs, dedicated oscillators and power gating solutions. The white paper also mentions PowerStudio, their GUI for configuring and controlling their low power elements. PowerStudio helps to verify the power management system as well. It offers a wide range of checks that cover power mode transitions, ICU responses, power mode coverage, ICU states, regulator model consistency, isolation, isolation control and retention.

The last portion of the white paper talks about benchmarking power consumption and efficiency. ULPMark-CoreProfile (ULPMark-CP) considers leakage current in sleep modes and active mode power consumption. Unlike peripheral power usage, MCU power varies significantly depending on the efficiency of the power management techniques that have been applied. Dolphin Design offers detailed results of benchmarking that compares the approaches mentioned above. From the baseline external PMIC to full utilization of all the methods that Dolphin Design supports there is a 2 orders of magnitude improvement of the ULPMark-CP numbers.

The Dolphin Spider platform promises to be extremely useful and efficient for the needs of ULP MCU designs. There is no doubt that the need for more efficient and longer life battery-based devices will continue to expand. Eliminating unneeded power consumption is the most cost-effective way to meet these market requirements. The full white paper is available on the Dolphin Design website and makes interesting reading on how a comprehensive power management system can deliver impressive results.

 

 

 

 


Comments

There are no comments yet.

You must register or log in to view/post comments.