Integrated Power Management IP to Decrease Power and Cost

Integrated Power Management IP to Decrease Power and Cost
by Eric Esteve on 09-19-2018 at 7:00 am

This blog is the synthesis of a white paper “New Power Management IP Solution from Dolphin Integration can dramatically increase SoC Energy Efficiency”, which can be found on Dolphin Integration web site.

The power consumption generated by complex chips was not a real issue when the system could be simply plugged in the wall to … Read More


Harnessing Clock and Power

Harnessing Clock and Power
by Alex Tan on 08-21-2018 at 12:00 pm

Switching translates to power. Similar to the recent slow down experienced by Moore’s Law, the constant power density (power demand per unit chip area) prescribed by Dennard scaling was no longer affordable across the technological scaling. While the contribution of leakage power component in advanced process nodes was getting… Read More


Design for Power: An Insider View

Design for Power: An Insider View
by Bernard Murphy on 06-28-2018 at 7:00 am

The second keynote at Mentor’s U2U this year was given by Hooman Moshar, VP of Engineering at Broadcom, on the always (these days) important topic of design for power. This is one of my favorite areas. I have, I think, a decent theoretical background in the topic, but I definitely need a periodic refresh on the ground reality from the… Read More


Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More


Webinar: Understanding Clock Gating Metrics for SpyGlass Power

Webinar: Understanding Clock Gating Metrics for SpyGlass Power
by Bernard Murphy on 09-07-2017 at 4:00 pm

Clock gating is one of the simplest ways to reduce dynamic power in a design. By turning off the clock on a register which is busy doing nothing useful you can eliminate pointless switching power in that register and also in much or all of the following fanout cone of combinational logic. In this way, judicious gating can extend battery… Read More


Checking Clock Gating Equivalence the Easy Way

Checking Clock Gating Equivalence the Easy Way
by Bernard Murphy on 07-14-2017 at 7:00 am

Synopsys just delivered a Webinar on using the sequential equivalence app (SEQ) in their VC Formal product to check that clock-gating didn’t mess up the functional intent of your RTL. This webinar is one in a series on VC Formal, designed to highlight the wide range of capabilities Synopsys has to offer in formal verification. They… Read More


Webinar: Synopsys on Clock Gating Verification with VC Formal

Webinar: Synopsys on Clock Gating Verification with VC Formal
by Bernard Murphy on 07-06-2017 at 12:00 pm

Clock gating is arguably the mostly widely-used design method to reduce power since it is broadly applicable even when more sophisticated methods like power islands are ruled out. But this style can be fraught with hazards even for careful designers. When you start with a proven-correct logic design and add clock gating, the logic… Read More


Low power physical design in the age of FinFETs

Low power physical design in the age of FinFETs
by Beth Martin on 09-30-2016 at 7:00 am

Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More


Sonics opens new strategy for SoC energy processing

Sonics opens new strategy for SoC energy processing
by Don Dingee on 05-09-2016 at 4:00 pm

Back in February when we shared the Sonics philosophy on the ICE-Grain Power Architecture for hardware-based SoC power management, I speculated we’d know more by DAC 2016. Sonics is hitting the road with a new live seminar coming to Silicon Valley this month and Austin during DAC – and the news is big.… Read More


Who will provide data center Soc of the future, Intel or Qualcomm ?

Who will provide data center Soc of the future, Intel or Qualcomm ?
by Eric Esteve on 03-29-2016 at 4:00 pm

Intel has been incredibly successful by designing high performance server SoC to address the data center market segment, and the chance to see the company loosing large market share is pretty low, at least in the short term. Now, if we look at the really long term, 2030 or even 2040, like did the Semiconductor Industry Association… Read More