SoC power management a study in transition latency

SoC power management a study in transition latency
by Don Dingee on 02-22-2016 at 4:00 pm

Apple’s recent bout with ‘Batterygate’ highlighted just how important dynamic power management can be. Our last Sonics update looked at using their NoC to manage power islands; this time, we look at their research progress on architectural measures for power management.… Read More


Networking through dark silicon power islands

Networking through dark silicon power islands
by Don Dingee on 12-27-2015 at 7:00 am

For decades, tracing back to the days of Deming, the way to tackle complex engineering problems has been the pareto chart. Charting conditions and their contribution to the problem leads to mitigation priorities.

In the case of SoC power management, the old school pareto chart said the processor core was the biggest power hog and… Read More


Power Reduction Verification Techniques Highlighted by Mentor at ARM Techcon

Power Reduction Verification Techniques Highlighted by Mentor at ARM Techcon
by Tom Simon on 11-24-2015 at 4:00 pm

Power management is a perennial topic these days, and it came up in several presentations at the recent ARM Techcon in Santa Clara in mid November. The techniques covered in these talks address dynamic and static power consumption. The IEEE 1801 standard deals with specifying power design intent in Universal Power Format (UPF)… Read More


A Comprehensive Power Optimization Solution

A Comprehensive Power Optimization Solution
by Pawan Fangaria on 04-20-2015 at 7:00 am

In an electronic world driven by smaller devices packed with larger functions, power becomes a critical factor to manage. With power consumption leading to heat dissipation issues, reliability of the device can be affected, if not controlled or the device not cooled. Moreover, for mobile devices such as smartphones or tablets… Read More


How to Reduce Maximum Power at RTL Stage?

How to Reduce Maximum Power at RTL Stage?
by Pawan Fangaria on 08-16-2014 at 8:30 am

Of course that reduction has to stay throughout the design cycle up to layout implementation and fabrication. Since the advent of high density, mega functionality SoC designs at advanced nodes and battery life critical devices played by our fingertips, the gap between SoC power requirement and actual SoC power has only increased.… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More


Clock Gating: Sequential Is Better

Clock Gating: Sequential Is Better
by Paul McLellan on 04-01-2013 at 3:46 pm

Sequential clock gating offers more power savings that can be obtained just with combinational clock gating. However, sequential clock gating is very complex as it involves temporal analysis over multiple clock cycles and examination of the stability, propagation, and observability of signal values.

Trying to do sequential… Read More


Watch the Clock

Watch the Clock
by Paul McLellan on 03-05-2013 at 2:24 pm

Clock gating is one of the most basic weapons in the armoury for reducing dynamic power on a design. All modern synthesis tools can insert clock gating cells to shut down clocking to registers when the contents of the register are not changing. The archetypal case is a register which sometimes loads a new value (when an enable signal… Read More


RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip!

RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip!
by Daniel Nenni on 02-06-2013 at 10:00 pm

Approximately 25% of SemiWiki traffic originates from search engines and the key search terms are telling. Since the beginning of SemiWiki, “low power design” has been one of the top searches. This is understandable since the mobile market has been leading us down the path to fame and fortune. Clearly lowering the… Read More


Sequential Power Optimization

Sequential Power Optimization
by Paul McLellan on 11-29-2012 at 8:44 pm

Calypto has an interesting webinar coming up about Minimizing RTL Power Through Sequential Analysis. It is next Tuesday December 4th at 11am.

Insert standard paragraph about how power is the new timing, everyone worries about power, battery life in smartphones, half-empty datacenters.

You probably already know about clock… Read More