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Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that consume about 2/3[SUP]rd[/SUP] of total chip power. So what? In a simplistic manner, it’s very easy to visualize the solution as, “gate the clock on registers to be active only when they are needed to drive any activity”. However, there are different tricky scenarios which need to be looked at in order to do it correctly. Also, imagine you discovered the clocks to be gated at the layout stage in a multi-million gate design, how difficult and expensive it would be modify the design?

What if we have a tool that can automatically identify the clocks to be gated at right places in right manner and at the earliest stage, i.e. RTL? SpyGlass Power is such a versatile tool that can find gating opportunities, estimate effectiveness in saving power, fix problems at RTL, and check the design for correctness and testability while providing other important features such as reporting various statistics (e.g. no. of enabled registers Vs. time graph, power enable score card, power saving report etc.) which can be utilized by the designers to make informed decisions.

Above is an example where upstream registers are gated while downstream registers are driven by free clock. Enable at the upstream registers can be delayed and used to gate the downstream registers as well without affecting the functionality.

Another example shows how a recursive approach is needed to find all clock gating opportunities in the design. By tracing forward from register ‘A”, gating opportunities at register “B” can be found, but not at “C” simultaneously. The gating opportunity at “C” can be found only after the opportunity at “B” has been found.

 How to determine whether a clock gating will really be effective in saving power? Considering this example, in order to save large power consumption in operators such as multipliers and comparators, one could think of adding clock gating at the upstream register, but that would mean duplicating the downstream enable logic at upstream enable also. This defeats the purpose of power saving. SpyGlass Power computes power consumed before and after gating and allows designers to implement only those gating scenarios that save power significantly, because gating has costs in terms of additional delay and more work for clock tree synthesis.

Another important, rather critical aspect to look at is that the clock gating must not introduce any meta-stability issues on Clock Domain Crossing (CDC) for asynchronous clocks. SpyGlass Power is intelligent enough to infer meta-stability issues and avoid them in order to implement only CDC-safe clock gating.

SpyGlass Power also helps synthesis tools (which use register width as a factor to implement clock gating) to avoid bad clock gating. It computes actual power saving due to enables and generates a “don’t touch” script for negative power opportunities which can be used by the designers to guide their synthesis tool appropriately.

A power enable scorecard report, like the one above, provides unique opportunity for a designer to look at the areas where there is more room for clock gating and also inefficient clock gating which does not save much power. “mc_cont” has ~98% of clock activity saving (with ~40% of registers gated), but still has 96 more new gating opportunities. An opposite scenario in “mc_rf” shows ~90% of registers gated, yet only ~1% of clock activity saving.

After finding the right opportunities to add clock gating, SpyGlass Power can fix them automatically in most commonly used RTL descriptions such as Verilog, SystemVerilog or VHDL. By looking at the detailed reports and highlighted schematics, a designer can also find more gating opportunities and fix them manually.

After fixing the code for gating all possible clocks, it becomes obligatory to re-verify the new power optimized RTL. It’s not wise to do a full blown simulation at this moment, nor a standard Logic Equivalence Checking (LEC) because it does not understand sequential changes. SpyGlass Power provides Sequential Equivalence Checking (SEC) that can verify the equivalence between original and new RTL much faster.

Above is a complete flow of power estimation, reduction, fix, and re-verification of RTL description in SpyGlass Power. Also, there is SpyGlass DFT DSM to further verify the clock gated design for correct propagation of test clocks through various modes such as scan shift, capture, and at-speed capture. SpyGlass CDC is another tool to verify a complete design to make sure there are no functional issues across asynchronous clock domains.

Guillaume Boillet and Kiran Vittal have described the overall scheme of operation in more detail with specific examples in their whitepaperposted at Atrenta website. I loved studying it and would recommend designers and semiconductor professionals to read it through and know more.

More Articles by Pawan Fangaria…..

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