Webinar: Getting to Formal Coverage

Webinar: Getting to Formal Coverage
by Bernard Murphy on 04-20-2017 at 10:00 am

Facing rapidly growing challenges in getting to respectable coverage, designers have been turning more and more to formal verification, not just to plug gaps but increasingly to take over verification of significant components of the testplan. Which is great, but at the end of the day any approach to verification must be measured… Read More


Checkout the Upcoming Synopsys Power Webinar

Checkout the Upcoming Synopsys Power Webinar
by Bernard Murphy on 09-09-2016 at 7:00 am

This is part 3 of a series of 4 on low power design, scheduled for September 21st at 10am. Kiran Vittal and Ken Mason will be discussing using the SpyGlass Power solutions (analysis and verification) to optimize power at RTL. Atrenta always had a leading position in this area; I expect a year following their acquisition by Synopsys,… Read More


Improve Test Robustness & Coverage Early in Design

Improve Test Robustness & Coverage Early in Design
by Pawan Fangaria on 11-03-2014 at 5:00 pm

In a semiconductor design, keeping the design testable with high test coverage has always been a requirement. However with shrinking technology nodes and large, dense SoC designs and complex logic structures, while it has become mandatory to reach close to 100% test coverage, it’s extremely difficult to cope with the explosion… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More