3DIC Design from Concept to Silicon 800X100
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3452
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3452
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

Improve Test Robustness & Coverage Early in Design

Improve Test Robustness & Coverage Early in Design
by Pawan Fangaria on 11-03-2014 at 5:00 pm

In a semiconductor design, keeping the design testable with high test coverage has always been a requirement. However with shrinking technology nodes and large, dense SoC designs and complex logic structures, while it has become mandatory to reach close to 100% test coverage, it’s extremely difficult to cope with the explosion of test patterns and keep them robust enough to detect each fault. While at-Speed or transition faults are more cumbersome to detect than stuck-at faults, at deep hierarchical logic levels the circuit becomes hard to test giving rise to another category called random resistive faults. Often a chip fails at the tester due to glitches in the design because of a non-robust test pattern. Trying to understand and correct these glitches can be a very time consuming situation.

Here is an example of the issues with test pattern robustness; while the test pattern generation tool assumes there is only one clock, the clocks merging at the ‘OR’ gate can cause a glitch on the tester. Similarly there can be other issues with deep logic circuits, especially in scenarios which can lead to merging of test clocks, re-convergent resets and so on. These kinds of issues need to be checked and avoided to make the test patterns more robust.

It was a nice occasion attending a webinaroffered by Kiran Vittal, Sr. Director, Product Marketing at Atrenta, where he presented details about SpyGlass DFT and SpyGlass DFT DSM products. These tools can be used very early in the design phase, at the RTL stage, to identify such issues, fix them, verify different aspects, and deliver improved RTL which will provide higher stuck-at and at-speed fault coverage along with more robustness and scannability in the design.

A designer can check for blocks with low coverage in the fault browser, and then a few schematics of the blocks to understand the issues and fix the RTL. The audit coverage report, for both stuck-at and transition faults, provides extremely useful information with existing coverage and actions to be performed to increase that coverage. Recently Atrenta added a smart capability in audit report where it checks for test robustness issues like merging clocks and re-convergent resets and pinpoints these in the report. For example, the various flops which could be the source for glitches are reported. With the help of this report, designers can save significant amounts of time and effort in fixing these issues at RTL, rather than leaving it for the downstream tools to debug later, which can take much longer, weeding through much more detailed data, while using far more expensive tools. A dashboardfor management review is also provided where management can set objectives and criteria to be achieved and then periodically review the progress and trend lines.

SpyGlass DFT identifies the positions in RTL where test points can be inserted to improve controllability and observability of particular nodes. It also reports the number of faults which can be detected after inserting these test points. To fix random resistive issues (described below), SpyGlass DFT DSM can trace throughthe hierarchy and identify test points to be inserted at the block boundaries. The random pattern coverage after applying test points are also generated for ‘what if’ analysis.

Random resistive faults are hard to test, because they are generally buried deep inside the design hierarchy. By zooming on color annotations and displaying the schematic, controllability and observability of nodes, in the range of lowest to highest, can be obtained and appropriate actions can be taken to fix low observability and controllability points. Random resistive faults have high impact on ATPG pattern count and runtime; and ATPG efficiency is especially poor for transition fault detection. SpyGlass DFT DSM reports random pattern coverage estimates in a hierarchical fault browser and helps designers through color annotation in schematics to fix specific faults to increase the coverage.

In an SoC, the DFT architecture can be quite complex and the test logic is controlled by the JTAG TAP controller. SpyGlass DFT runs at block level as well as SoC level and validates block level constraints that must be satisfied at the SoC level. It treats the block as a black box and verifies if correct ‘test mode’ values are reaching the block, thus allowing the processing in a top down manner early in the cycle.

To aid complex initialization with JTAG/IEEE 1500 controllers, SpyGlass DFT provides more effective and easier debugging of test sequences through Tcl commands and assertions. For easy debugging of failed assertions, the logic is highlighted in RTL and the issue is highlighted in the schematic, all in a single GUI. The expanded bit-sequence and waveform view can also be seen. This does not require writing time consuming testbenches; applying structural rules at RTL and some assertions to quickly verify connectivity for different modes of operations are sufficient. Verifying different types of faults and connectivity can be done very early in the design phase.

Another interesting and very effective solution from Atrenta is SoC test signoff with Abstract Modelsof IP which provides significant improvement (~2-6x) in runtime and memory compared to flat flow. SpyGlass also provides automatic insertion of memory test and repair at RTL; it supports vendor independent, user supplied MBIST at RTL.

The RTL test signoff meets many important design requirements such as scannability, stuck-at and transition test coverage goals and test robustness much earlier in the design flow and much faster (~10x faster than post layout). Kiran also talked about a customer case on a mobile application where they achieved ATPG test coverage for stuck-at faults within ~1% of what was reported by SpyGlass at RTL (>99%). The RTL estimation vs. transition ATPG correlation was within ~5%. The average runtime speedup of RTL compared to netlist ATPG was ~30x. View the on-demand webinarposted at Atrenta website to learn more.

More Articles by Pawan Fangaria…..

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.