Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up

Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
by Admin on 06-15-2022 at 10:00 am

Synopsys Webinar | Wednesday, June 15, 2022 | 10:00 – 10:30 a.m. Pacific

Electronic systems in automobiles are growing rapidly in size, complexity, and critical functionality. As a result, functional safety verification is emerging as an essential requirement for automotive SoC and IP designs. In order to assure that

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Analog Fault Injection Simplifies ISO 26262 Compliance

Analog Fault Injection Simplifies ISO 26262 Compliance
by Admin on 03-17-2022 at 12:00 am

Overview

As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. With these complex designs, designers will require automation to overcome the limits of using expert… Read More


Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression… Read More


Improve Test Robustness & Coverage Early in Design

Improve Test Robustness & Coverage Early in Design
by Pawan Fangaria on 11-03-2014 at 5:00 pm

In a semiconductor design, keeping the design testable with high test coverage has always been a requirement. However with shrinking technology nodes and large, dense SoC designs and complex logic structures, while it has become mandatory to reach close to 100% test coverage, it’s extremely difficult to cope with the explosion… Read More