This is part 3 of a series of 4 on low power design, scheduled for September 21st at 10am. Kiran Vittal and Ken Mason will be discussing using the SpyGlass Power solutions (analysis and verification) to optimize power at RTL. Atrenta always had a leading position in this area; I expect a year following their acquisition by Synopsys, they must have further solidified their position, based on how well I hear the acquisition is working out. I’m very familiar with what Synopsys has to offer here, since I was at Atrenta for many years – we were rapidly displacing competitive solutions so I expect that story continues, now a year into the acquisition :cool:.
Design for low power is a complex problem spanning system architecture and application software all the way down to design process and library selection. This series looks at multiple aspects of the RTL design problem:
- (Part 1): Static checking for the RTL (for correct and consistent UPF specification for example) and simulation to detect potential dynamic conflicts
- (Part 2): Using Verdi power-aware debug to catch power bugs
- (Part 3 – this upcoming Webinar): Optimizing your power design through power estimation and finding opportunities to further reduce power
- Atrenta led the field in accuracy in power estimation at RTL, thanks to obsessive work on correlating accuracy of our fast synthesis with physical synthesis, in matching macro choices, clock and signal buffering and building correlation databases against implemented designs. Still, this is always a bit of a challenge when you don’t also own the physical synthesis tools. Acquisition by Synopsys solved that problem so correlation can only have improved further. We also had very strong solutions in micro-architecture optimization for low-power (formally detecting and proving ways to add or strengthen gating based on initial user choices) and what-if analysis to guide improved user-selection of Vt mixes, power gating, macro-level clock-gating and all the rest of the spectrum of power-control options.
- (Part 4): Using Verdi technologies (Siloti correlation and replay simulation) to bridge between RTL simulation data and gate-level accuracy
If you still think low power design is just about specifying clock gating pragmas for synthesis, take a deep breath. Low power design, as supported by these kinds of analysis, has become a major area for differentiation with many dimensions and multiple opportunities to make very good or very bad choices. The broad palette of low-power design solutions, connected to implementation technologies, is a big part of why Synopsys has such strength and depth in this area. You need to know what methods and tools are being used in the industry today to help you stay at the forefront of competitive low-power design.
Web event: SpyGlass Power: Comprehensive Power Optimization Solution for Faster RTL Signoff (Part 3 of 4)
Date: September 21, 2016
Time:10:00 AM PDT
Duration: 60 minutes
In an electronic world driven by smaller devices packed with larger functions, power becomes a critical factor to manage. With power consumption leading to heat dissipation issues, reliability of the device can be affected, if not controlled or the device not cooled. Moreover, for mobile devices such as smartphones or tablets that run on battery, low power consumption is essential. For a holistic solution to the power problem, it is important that this is addressed at the source, i.e. the RTL design stage.
In this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration. SpyGlass Power leverages the industry leading SpyGlass Platform and GuideWare methodology for an easy to use and comprehensive flow for RTL signoff.