Dr. Zakir Syed is Co-founder and Chief Technology Officer of ClockEdge, where he has played a central role in developing specialized simulation technology for advanced semiconductor clock networks. He brings more than 30 years of experience in electronic design automation and semiconductor verification. He joined Simplex Solutions near its inception in 1995, contributing to technologies addressing timing, power, signal integrity, and reliability.
Zakir has published numerous technical papers on verification and simulation and presented at industry conferences. He holds a master’s degree in Mechanical Engineering and a PhD in Electrical Engineering, both from Duke University.
What brought you to ClockEdge?
Earlier in my career at Simplex Solutions, I worked on technologies for analyzing large electrical networks. One of the recurring challenges was maintaining transistor-level accuracy as designs grew increasingly complex.
Clock networks were particularly interesting because they are the most critical distribution networks in a synchronous SoC. An SoC has multiple clocks, and together their networks reach every sequential element. In high-performance processors, clock distribution can account for roughly 30% of total chip power.
Yet even small variations in clock behavior can have significant consequences for performance and reliability. Analyzing the entire network with conventional transistor-level simulation was simply too computationally expensive for practical use on large SoCs.
We saw an opportunity to develop simulation technology specifically for clocks, combining SPICE-level accuracy with the speed and capacity needed for large designs.
That became the technical foundation of our work at ClockEdge. Today, the opportunity goes beyond accurate analysis to helping engineers use that insight to improve performance, power, and reliability.
What is the biggest challenge your customer is facing?
Our customers are being asked to deliver higher performance with lower power while ensuring their chips operate reliably in silicon. At advanced nodes, that balance is becoming increasingly difficult.
Timing margins are tighter, and electrical effects that might once have been relatively small can now have a significant impact. Power-supply noise, for example, can shift clock edges and change the relative timing between clock paths. Waveform distortion and duty-cycle changes can further reduce the usable timing window.
Engineers compensate for uncertainty by adding timing margin. That is necessary, but excessive margin can come at a substantial cost in frequency, power, or area.
The difficult question is how much of that margin is actually needed.
Customers want to distinguish real electrical risks from conservative assumptions. The better they understand that difference, the more confidently they can pursue aggressive PPA targets without compromising silicon reliability.
Why is your approach to solving this problem unique?
We developed simulation technology specifically for clock networks, rather than adapting a general-purpose simulator.
By exploiting the characteristics of clock-network topologies, we can analyze complete clock networks, including complex trees and meshes, with SPICE-level electrical accuracy and the speed and capacity needed for large SoCs.
Our technology works with industry-standard design data and fits alongside existing implementation and sign-off flows, allowing engineers to introduce detailed electrical analysis without replacing their established tools.
Our Veridian platform brings together timing, jitter, power, and aging analysis. It allows engineers to examine how electrical effects interact across the network, rather than considering each one in isolation.
But identifying a problem is only part of the job. Engineers also need to know how best to address it.
That’s where vHelm comes in. It connects electrical analysis with interactive what-if exploration and Virtual ECOs.
Consider resizing a clock buffer to improve timing. That change may also affect power consumption, waveform quality, or jitter elsewhere in the network. With ClockEdge, engineers can examine those trade-offs before committing to a physical design change.
The objective is to make accurate electrical analysis useful for everyday design decisions, not just final verification.
What other approaches are being used to solve this problem?
Design teams already use sophisticated tools for static timing analysis, power integrity, clock integrity, and circuit simulation. They also rely on statistical methods and guardbanding to manage uncertainty.
These approaches serve important purposes, and modern EDA tools can analyze many of the electrical effects we’re discussing.
The challenge is translating all that information into the best possible clock implementation.
A design may meet its timing constraints and still have unnecessary buffering, excess clock power, or more margin than its actual electrical behavior requires. Identifying those opportunities and understanding the consequences of possible changes can involve considerable analysis and iteration.
This is where we believe ClockEdge offers a valuable approach. By combining full-clock electrical analysis with interactive optimization, engineers can investigate alternatives and evaluate their impact across timing, jitter, power, and aging in one flow.
Meeting timing requirements tells you that a design satisfies its constraints. It doesn’t necessarily tell you whether you’ve achieved the best possible performance and power efficiency.
That’s the opportunity we want to help engineers explore.
What challenges will your customers face in the near future?
I expect the interaction between transistor behavior, power delivery, and clock performance to become increasingly important.
The transition to gate-all-around transistors at 2nm and beyond, along with innovations such as backside power delivery, are creating new opportunities for performance and power efficiency. These technologies also change the electrical characteristics and design conditions engineers need to understand.
At the same time, AI and high-performance computing are driving demanding performance-per-watt requirements. Designs have increasingly complex operating modes, power-management strategies, and workloads that can change electrical conditions dynamically.
Engineers will need to understand how clock networks behave across these conditions, including the effects of supply noise, process variation, and transistor aging over the product’s lifetime.
I also see a broader change in design methodology.
Detailed electrical analysis has traditionally been concentrated toward the later stages of implementation. Making that insight available earlier allows engineers to make better choices about clock architecture, buffering, and optimization, rather than discovering problems when changes have become expensive.
How has AI changed your business strategy?
AI has reinforced the importance of what we’re doing while opening up new possibilities for how we approach the technology.
On the customer side, AI accelerators and high-performance computing systems are pushing performance and power requirements to new levels. That makes clock efficiency and accurate electrical analysis increasingly important. Even small improvements can matter when designs are operating close to their limits.
Within our own technology, we’re investigating how machine learning can complement circuit simulation. One area of interest is neural-network surrogate modeling for clock jitter, where models trained against detailed electrical simulations could help make certain types of analysis more efficient.
I don’t see AI replacing physics-based simulation. Semiconductor designers still need to know that their results reflect actual circuit behavior.
Where I see significant potential is in using AI to guide design exploration, identify promising alternatives, and focus detailed simulation where it adds the most value.
The combination of intelligent exploration and rigorous electrical analysis could allow engineers to consider more design options and make better decisions much earlier in the process.
Also Read:
The End of “Good Enough” Timing Analysis
WEBINAR: Reclaiming Clock Margin at 3nm and Below
What is the 3nm Pessimism Wall and Why is it An Economic Crisis?
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