Intel Foundry: AI performance now depends on the whole system

For decades, chipmakers improved computing performance largely by putting more capable circuitry on a piece of silicon. That remains important, but AI is exposing its limits. Large models demand enormous amounts of data movement, sustained power and effective cooling. A fast processor cannot deliver its full benefit if memory cannot feed it quickly enough or heat forces it to slow down.

In a September 2026 article, Intel Foundry’s Lalitha Immaneni argues that the next gains will come from designing silicon, packaging, circuit boards and the wider platform as one system, to which I agree with 100%. Advanced packaging is central to that approach. Once chiefly a way to protect a finished chip and connect it to a board, the package now helps determine how processors communicate with memory, how power reaches them and how heat escapes.

One way to build such systems is to divide a large design into smaller chiplets. Different chiplets can perform different jobs and can be made with the manufacturing processes best suited to each. Designers may be able to reuse existing components, combine technologies and build products that would be impractical as a single piece of silicon. But dividing a chip creates new questions: where should each function go, how should the pieces connect and what will those connections cost in power, space and speed?

Those questions matter especially for AI hardware. A processor might be capable of more calculations than its memory connection can support. Moving components closer together may improve communication while concentrating heat. A package that works electrically may prove difficult to manufacture reliably. Improving one part of the design can worsen another, so the best choice often becomes clear only when the complete system is evaluated.

Immaneni calls for that evaluation to begin early. Before committing to a design, teams should compare ways to divide functions among chiplets, choose manufacturing processes, route connections and integrate memory. They also need to test likely effects on temperature, power delivery, manufacturing yield and cost. Discovering a problem while exploring designs is far less disruptive than finding it after detailed layouts or physical prototypes are complete.

Connections between chiplets are a case in point. They require more than a shared communication specification. The positions and spacing of physical contacts must fit the package, and engineers must establish that signals work under real operating conditions. If chiplets from different suppliers are to combine easily, compatible interfaces, reliable design information and validated components will be essential. Otherwise, each new combination risks becoming a costly custom project.

Heat and power add further constraints. AI systems can operate near peak activity for long periods, creating concentrated hot spots. The location of chiplets and the materials around them affect cooling. Likewise, the path that delivers electricity through the board, package and silicon affects how much performance a system can sustain. These are architectural choices, not finishing touches.

That changes how engineers must work together. In a largely sequential process, chip designers could make decisions and pass a design to package and board teams later. Tightly integrated systems require those groups to compare options and resolve conflicts throughout development. Better simulation, experimentally checked models and digital representations of proposed systems could help teams predict problems before building expensive hardware.

Intel Foundry points to its packaging technologies and supporting design tools as part of this effort. The broader challenge, however, reaches beyond any one supplier. Foundries, packaging specialists, software toolmakers, memory suppliers and customers need ways to exchange trustworthy design information and make components work together.

Bottom line: Demand for AI computing is rising, but more processing circuitry alone cannot solve limits in bandwidth, energy use and heat. Designing the whole system together could yield faster, more efficient products and reduce late redesigns. Intel Foundry’s focus on system-level co-design and ecosystem collaboration reflects this industry shift. The approach will succeed only if engineers can model those interactions accurately and make chiplets practical to combine at scale.

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