Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon

Akhilesh Kumar & Krishnakanth Sistla, Intel

Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional monolithic mesh with a fan-out fabric connecting modular compute building blocks to centralized fabric hubs. This functional partitioning separates scalable core resources from memory, I/O, acceleration, and coherence services, enabling Intel to expand capacity without forcing every subsystem onto one enormous die.

The design extends Intel’s progression from ring and planar mesh organizations through tiled and modular meshes toward a three-dimensional mesh. Its objective is balanced system throughput: stronger per-thread execution, higher performance per watt, integrated AI and infrastructure acceleration, scale-up connectivity, and layered security with resilient reliability, availability, and serviceability.

Each compute building block combines a base tile with as many as four core chiplets. A core chiplet contains up to 16 performance cores and private L2 caches, while a three-dimensional crossbar connects those cores to shared last-level cache on the base tile. Caching agents and snoop filters maintain coherency within the building block. Diamond Rapids integrates four compute building blocks, sixteen core chiplets, and four base tiles, yielding up to 256 cores and 1.28 GB of aggregate LLC.

The packaging system combines 2.5D and 3D integration. Core chiplets attach to base tiles through Foveros 3D Direct hybrid bonding, whereas four base tiles and two fabric-hub tiles communicate across the package substrate using UCIe-S copper links. This construction lets compute density scale vertically while bandwidth-intensive system functions scale laterally. The processor uses Intel 18A-P, an enhanced process offering a dual-contact, low-resistance PowerBoost option, an additional threshold-voltage choice, tighter skew corners, and reduced thermal and via resistance.

Fabric hubs centralize memory and I/O. The unified memory fabric supports sixteen channels, DDR5 at up to 8,000 MT/s, MRDIMMs at up to 12,800 MT/s, and aggregate bandwidth approaching 1.6 TB/s. Memory controllers provide ECC, row-hammer protection, and power management. Memory Value Functions support CXL memory in one-level or Flat 2LM modes plus mirroring, while encryption engines protect either DDR or CXL memory. Moving directory state from DRAM into on-die home snoop filters preserves complete ECC coverage, reduces lookup latency and coherence traffic, and simplifies memory organization.

The Flexbus I/O fabric exposes four groups of sixteen high-speed lanes per fabric hub. Each x16 group can implement PCIe 6.0, CXL 3.0, UPI 3, or supported combinations. Across the socket, Diamond Rapids provides 128 high-speed lanes with up to 2 TB/s of bidirectional bandwidth, plus eight PCIe 4.0 lanes for platform infrastructure. Up to 16 MB of I/O cache and on-die filtering support coherent data movement. Every fabric hub also contains two accelerator complexes integrating QuickAssist Technology, Data Streaming Accelerator, and In-Memory Analytics Accelerator engines.

Power management follows the functional partitioning. Separate dynamic-voltage-and-frequency domains govern cores, compute-building-block uncore logic, I/O, and memory. A new idle state retains L2 contents, reducing restart penalties, while Priority Core Turbo directs frequency headroom toward latency-sensitive work. MR4-based memory thermal controls, L0p support on UXI and PCIe links, and workload-aware power steering further improve efficiency.

At the instruction level, Diamond Rapids supports Intel Advanced Performance Extensions. APX adds sixteen general-purpose registers for a total of 32, three-operand instructions with a new-data-destination form, conditional operations, flag suppression, 64-bit absolute branches, and XSAVE support. Existing x86 binaries remain compatible, while recompilation can exploit the expanded register state. AI computation is accelerated through AMX and AVX 10.2 with FP8, FP16, and BF16 support.

Security and reliability remain architectural requirements rather than peripheral features. Intel TDX, TDX Connect, and SGX provide multiple isolation mechanisms, while memory encryption, on-die coherence directories, enhanced telemetry, and RAS features protect large systems. Diamond Rapids therefore advances Xeon through modularity: dense 3D compute, centralized coherent fabrics, extreme memory and I/O bandwidth, specialized acceleration, and independent power control combine into a platform aimed at agentic AI and data-intensive infrastructure.

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