Andes Webinar (China) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Andes Webinar (China) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
by Admin on 01-15-2024 at 4:28 pm

Description

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications… Read More


Andes Webinar (EMEA and Japan) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Andes Webinar (EMEA and Japan) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
by Admin on 01-15-2024 at 4:26 pm

Description

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications… Read More


Webinar: Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Webinar: Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
by Admin on 01-08-2024 at 2:03 pm

Description

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications… Read More


Webinar: Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study

Webinar: Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
by Admin on 09-06-2023 at 2:19 pm

Synopsys Webinar | Thursday, September 21, 2023 | 10:00 a.m. Pacific

The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions.

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Webinar: Using Formal Datapath Validation to Verify AI Processor Computations hosted by Synopsys

Webinar: Using Formal Datapath Validation to Verify AI Processor Computations hosted by Synopsys
by Admin on 12-14-2022 at 1:46 pm

Summary

For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs.

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Embedded Applications Get a Helping Hand: Extensible Processor Architectures

Embedded Applications Get a Helping Hand: Extensible Processor Architectures
by Admin on 05-17-2022 at 4:29 pm

Synopsys Webinar | Tuesday, June 7, 2022 | 10:00 – 11:00 a.m. PDT

Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial

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