The Pelican Has Landed: Formal on an Unannounced ARM Processor

The Pelican Has Landed: Formal on an Unannounced ARM Processor
by Paul McLellan on 11-10-2013 at 3:00 pm

At the Jasper Users’ Group, Alex Netterville of ARM presented about how ARM are using formal on an unannounced processor code-named Pelican. Don’t read the presentation trying to find out information about Pelican itself, there isn’t any. That wasn’t the topic. Alex has been using formal approaches… Read More


Synopsys Creates a High-performance ARC Core

Synopsys Creates a High-performance ARC Core
by Paul McLellan on 11-05-2013 at 10:00 am

ARC is a family of configurable processors. Originally it was a standalone company in the UK (what is it with the UK and processor cores?) spun out from Argonaut Software. The A in ARC stood for Argonaut originally. ARC International was acquired by Virage and then Virage was acquired by Synopsys so now it is part of Synopsys Designware… Read More


Server Shift to ARM Becomes a Stampede

Server Shift to ARM Becomes a Stampede
by Paul McLellan on 10-19-2013 at 3:00 pm

I have been at the Linley Microprocessor Conference today. This is the one that is not about mobile: about servers, networking, base-stations. Probably the most important story about the whole industry is that the “shift to ARM becomes a stampede.”


In this market it seems to be driven by the 64-bit ARMv8 instruction… Read More


Putting the Ten in Tensilica

Putting the Ten in Tensilica
by Paul McLellan on 10-17-2013 at 3:55 pm

Chris Rowen of Cadence’s Tensilica announced the tenth generation of the Xtensa customizable processor at the Linley Microprocessor Conference yesterday. Chris was one of the founders of Tensilica…back in 1997. I believe that the first version was released in 1999. Over the years the Tensilica business changed.… Read More


Enter the Warrior

Enter the Warrior
by Paul McLellan on 10-14-2013 at 11:57 am

Since Imagination’s acquisition of MIPS at the end of last year, the MIPS product line has been given a new lease of life. There are two things driving this. The first is simply that with its new home, the MIPS architecture has a solid future whereas before it was uncertain. Secondly, Imagination moved their own general purpose… Read More


Imagination Has More Stuff Than You…Imagine

Imagination Has More Stuff Than You…Imagine
by Paul McLellan on 08-29-2013 at 1:04 pm

Imagination seems to be well known for a couple of things. Firstly, everyone knows that it is the graphics processor used in the iPhone and the iPad and lots of other phones. And they know that Imagination acquired MIPS at the start of this year.

But what people don’t seem to really appreciate is just what a huge portfolio of IP… Read More


How to Benchmark a Processor

How to Benchmark a Processor
by Paul McLellan on 08-15-2013 at 2:11 am

How do you benchmark a processor? It seems like it should be easy, just run some code and see how fast it is. Traditionally processors were indeed benchmarked by raw performance like GMACS, GFLOPS, memory bandwidth and so on. But in today’s world where systems have become very complex and applications very compute intensive, the… Read More


The Return of the "Moore Noyce" Company

The Return of the "Moore Noyce" Company
by Ed McKernan on 06-04-2013 at 7:00 pm

It has been a little over a fortnight since Paul Otellini officially stepped down from the CEO post and yet it seems to be more than a long time gone. Unlike his predecessors, he was not asked to remain on the board and perhaps it is a sign that his complete disengagement from the company was necessary to complete a future strategic engagement.… Read More


IP Wanna Go Fast, Core Wanna Not Rollover

IP Wanna Go Fast, Core Wanna Not Rollover
by Don Dingee on 08-23-2012 at 8:15 pm

At a dinner table a couple years ago, someone quietly shared their biggest worry in EDA. Not 2GHz, or quad core. Not 20nm, or 450mm. Not power, or timing closure. Call it The Rollover. It’s turned out to be the right worry.

Best brains spent inordinate hours designing and verifying a big, hairy, heavy breathing processor core to do … Read More


I/O Bandwidth with Tensilica Cores

I/O Bandwidth with Tensilica Cores
by Paul McLellan on 08-17-2012 at 3:00 pm

It is obviously a truism that somewhere in an SoC there is something limiting a further increase in performance. One area where this is especially noticeable is when a Tensilica core is used to create a highly optimized processor for some purpose. The core performance may be boosted by a factor of 10 or even as much as 100. Once the core… Read More