Data Center Energy Trends Force a Rethink of Chip Power Delivery

Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary:

Artificial intelligence is changing the requirements for semiconductor innovation. Faster transistors and denser packaging remain essential, but their benefits increasingly depend on another engineering challenge: delivering stable power to the places where computation happens. Intel Foundry’s two-part series on power delivery explains why electricity distribution and voltage regulation are becoming central to the future of data center performance.

The scale of projected demand makes this shift significant. In the first article, Intel Foundry cites Gartner estimates that worldwide data center power demand will rise from 104 gigawatts in 2025 to 132 gigawatts in 2026, reaching 290 gigawatts by 2030. AI-optimized servers are expected to account for 31% of consumption in 2026 and surpass conventional servers by 2027.

These are forecasts, but they highlight a practical constraint: computing expansion depends on available electricity and cooling capacity. Operators must divide limited power budgets among processors, memory, networking, and storage. Improving how electricity travels through compute hardware could help increase useful output within those budgets. That makes power delivery relevant to infrastructure economics as well as chip design.

Conventional frontside power delivery routes electricity and signals through shared metal layers. As designs become more complex, those functions compete for space. Rising current increases voltage losses through resistance, while inductance complicates responses to sudden workload changes. Engineers compensate with wider connections, additional capacitors, and operating margins, consuming resources and potentially sacrificing efficiency to maintain reliable operation.

Intel Foundry’s RibbonFET Gate-all-around (GAA) transistor architecture with Intel 18A, separates these functions by moving power routing to the chip’s backside. Dedicated power layers create shorter paths to transistors and free frontside resources for signals. Intel says this arrangement reduces resistance, inductance, and IR drop, the voltage lost as current passes through resistance, while improving the stability of the supply.

Local energy storage complements that architecture. Intel Foundry describes Omni MIM on-die capacitors, substrate-embedded capacitors with through-silicon vias, and embedded deep trench capacitors. These components provide nearby charge when demand suddenly increases. For bursty AI inference and high-performance computing workloads, that support can help limit brief voltage dips that otherwise threaten timing or require more conservative operating settings.

The second article extends the problem to chiplets and stacked dies. Combining multiple dies enables greater bandwidth and functional integration, but also concentrates current demand and increases the number of voltage domains. Package connections must carry power alongside dense signal traffic. Consequently, advanced packaging can create electrical bottlenecks even as it solves other constraints on performance scaling.

Intel Foundry’s response is to move voltage conversion closer to the load. Distributing power at a higher voltage reduces the current required to carry a given amount of power; conversion near the compute die then supplies its lower operating voltage. This approach can reduce distribution losses, although its overall benefit depends on regulator efficiency and the complete delivery network.

The authors describe several implementations. Fully integrated voltage regulators place the final conversion stage on the processor, supported by CoaxMIL magnetic inductors designed for higher current density. Continuous capacitive voltage regulators, or C2VR, use capacitors instead of traditional inductors. Dedicated regulator chiplets offer placement flexibility, including beneath compute dies or within package structures, potentially shortening demanding power distribution paths.

Why it matters is the connection between electrical stability and usable performance. A processor cannot consistently exploit its capabilities if supply voltage fluctuates beyond acceptable limits. Better routing, localized charge storage, and nearby regulation could reduce the margins required for safe operation. That creates opportunities for more efficient computing, while helping designers manage increasingly complex systems.

Bottom line: Scaling computation now requires coordinated advances across transistors, wiring, capacitors, regulators, and packaging. Power delivery is becoming a decisive factor in whether additional silicon produces worthwhile performance within increasingly constrained energy budgets.

Driving Power Delivery Innovations for the AI Data Center Era

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