Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in ComputingThe Global Semiconductor Alliance will present Micron Technology…Read More
NIST Sets a Clearer Course for the Post-Quantum Security TransitionNIST’s report, Transition to Post-Quantum Cryptography Standards, gives…Read More
CTO Interview with Ed Plowman of Imagination TechnologiesEd Plowman is Chief Technology Officer at Imagination…Read More
Ceva’s next NeuPro generation opens new possibilities across AICeva is broadening the possibilities for AI silicon…Read More
Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.
This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.
This year they’ve… Read More
The recent announcement from Arteris that iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems is very interesting, as it shows that SoC designed for the Automotive market segment also require advanced … Read More
Automation for digital design has been mainstream for a couple of decades but place and route for analog is still in its infancy. Many attempts have been made over the years to automate analog design in one way and another, the bodies are piled up on the hillside. Much analog design is still largely done with custom layout and circuit… Read More
The recent announcement from CEVA that it has joined the Wi-Fi Alliance® to further advocate for a software-based Wi-Fi® strategy shows that the new CEVA-XC4000 DSP can be used in various communication protocols, not limited to the traditional baseband processing for the wireless handset phone, where DSP IP core usage is massive.… Read More
The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the… Read More
Four years ago, a VC friend of mine was invited to a get together with a prominent Hedge Fund Manager from the Midwest. The meeting was an arrangement between fellow Harvard Grads. The Fund Manager was looking to make investments in the valley, to diversify away from his heavily weighted financial positions. Though, not recognized… Read More
Since the last Intel logo parody went over so well here is another one! Not so much a parody in light of the recent PR from Intel that the fabless semiconductor business model is doomed. As one of the doomed little people inside the fabless ecosystem I take exception to this but I digress….
The word around Silicon Valley is that Intel … Read More
You are in San Francisco for DAC and you want a coffee. OK, if your booth duty is 5 minutes away you pretty much have to take the Moscone coffee. Tastes good, hot, has caffeine. As Meatloaf used to sing (showing my age here) two out of three ain’t bad.
Yes, there are Starbucks all over the city, one on 4th Street just by Moscone Center,… Read More
AVNET released their 15[SUP]th[/SUP] Xfest this year, a couple of months ago. It was here in Germany last week. It was a well organized event, rich with invaluable technical information and full of decent smart engineers and managers. If you missed it this year register for the next event as soon as you can.
It was a very successful… Read More
EDAC has a series of seminars for emerging companies with Jim Hogan. Jim has been in EDA since, like, forever. First at National, then at Cadence, then at Artisan (now ARM) and then as an investor first at Telos (Cadence’s VC arm) and more recently on his own at Vista Ventures. He has been involved with many EDA and semiconductor… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival