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Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity  

Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity  
by Admin on 11-04-2026 at 10:00 am

By Defacto Staff

Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More


Reimagining 3D IC Design: From Architecture to Signoff

Reimagining 3D IC Design: From Architecture to Signoff
by Admin on 11-04-2026 at 8:00 am

figure1 digital twin creation

By Keith Felton, Andras Vass-Varnai and Todd Burkholder, Siemens EDA

The semiconductor industry is undergoing a fundamental transformation. Heterogeneous integration, the practice of combining multiple chiplets and specialized components into a single advanced packaging platform, has emerged as a powerful alternative… Read More


GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in Computing

GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in Computing
by Daniel Nenni on 11-04-2026 at 7:00 am

GSA Honors Sanjay Mehrotra

The Global Semiconductor Alliance will present Micron Technology Chairman and CEO Sanjay Mehrotra with its 2026 Dr. Morris Chang Exemplary Leadership Award, recognizing a career that connects foundational flash memory innovation with the demands of modern computing. The presentation is scheduled for GSA’s Annual Awards… Read More


NIST Sets a Clearer Course for the Post-Quantum Security Transition

NIST Sets a Clearer Course for the Post-Quantum Security Transition
by Daniel Nenni on 11-04-2026 at 6:00 am

NIST’s Post Quantum Migration Roadmap

NIST’s report, Transition to Post-Quantum Cryptography Standards, gives government agencies and technology suppliers a clearer framework for replacing cryptography vulnerable to future quantum computers. Its significance extends beyond selecting algorithms: it connects security priorities, application requirements… Read More


CTO Interview with Ed Plowman of Imagination Technologies

CTO Interview with Ed Plowman of Imagination Technologies
by Daniel Nenni on 11-03-2026 at 12:00 pm

Turning TOPS into useful work

Ed Plowman is Chief Technology Officer at Imagination Technologies, where he leads technology strategy, advanced architecture research and long-term innovation initiatives. He focuses on the convergence of graphics, compute and artificial intelligence, helping shape the next generation of efficient and adaptable computing… Read More


IP update from Alphacore at DAC 2026

IP update from Alphacore at DAC 2026
by Daniel Payne on 11-03-2026 at 10:00 am

alphacore at dac 2026

Rusafa Shahreen, Director of Technical Marketing at Alphacore met with me at DAC 2026 to provide an update on what’s new in their IP for AMS, RF, imaging and rad-hard designs. Her background includes MSEE and MBA degrees, plus seven years at Alphacore in Arizona. The founders of the company have a rad-hard background and their early… Read More


Ceva’s next NeuPro generation opens new possibilities across AI

Ceva’s next NeuPro generation opens new possibilities across AI
by Daniel Nenni on 11-03-2026 at 8:00 am

CEVA NEUPRO NPU portfolio

Ceva is broadening the possibilities for AI silicon with a new generation of its NeuPro neural processing unit portfolio, bringing a common architecture and unified software environment to applications spanning sensors, intelligent devices and cloud infrastructure.

Announced on October 28, the portfolio reflects an opportunity:… Read More


How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB Live

How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB Live
by Daniel Nenni on 11-03-2026 at 6:00 am

How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB Live

Allegro MicroSystems’ experience with yieldHUB Live shows how better use of production data can translate into measurable manufacturing gains. At its high-volume semiconductor operation in the Philippines, Allegro set out to improve overall equipment effectiveness, or OEE, by one percentage point. According to the customer… Read More


Interview with Sweta Gupta, VP of Engineering of Analog Bits

Interview with Sweta Gupta, VP of Engineering of Analog Bits
by Daniel Nenni on 11-02-2026 at 12:00 pm

Sweta Gupta in analog innovation

Sweta Gupta is the Vice President of Engineering at Analog Bits, where she leads development and execution of mixed-signal IP’s, managing circuit and layout teams.

Ms. Gupta has been a part of the Analog Bits team since 2004 and she has successfully managed and delivered high quality IP’s including low jitter PLL’s, low power crystal… Read More


WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs

WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs
by Daniel Nenni on 11-02-2026 at 10:00 am

Edge GPU AI webinar banner

Modern AI models are opening up new possibilities at the edge. Turning those possibilities into responsive, efficient applications, however, requires more than choosing hardware with an impressive TOPS figure. Developers need to understand how models behave on their target devices, where performance is lost, and which optimisations… Read More