As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently hosted its annual Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, CA. During the keynote address, TSMC executives highlighted the significant advances that have been accomplished through ecosystem alliances and collaborative efforts since last year’s event.
Specifically, significant strides have been made in multi-die system innovation initiatives, including the unveiling of 3Dblox 2.0 (the 3rd generation of 3Dblox), the formation of 3Dblox committee and the expansion of its 3DFabric Alliance to 21 partners. The 3Dblox Committee is an independent standard group aimed at creating industry-wide specifications for system design with chiplets from any vendor. The 3DFabric Alliance now has subgroups collaborating on design, memory, substrate, testing, manufacturing and packaging. These developments highlight TSMC’s commitment to advancing 3D IC technologies and fostering industry collaboration to drive innovation in AI, HPC, and mobile applications. And the commitment is reflected in the following quote from Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. “As our sustained collaboration with OIP ecosystem partners continues to flourish, we’re enabling customers to harness TSMC’s leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications.”
The event was marked by many insightful presentations that showcased the collaborative efforts between TSMC and various OIP ecosystem partners in accelerating semiconductor innovation. As the Silicon to Software™ partner for companies developing electronic products and software applications, Synopsys made a number of announcements recently. This article shines a spotlight on how Synopsys’ collaborative efforts with TSMC and other ecosystem partners unleashes innovation for customers as well as the entire ecosystem.
Certified Flows for TSMC N2 Process Accelerate 2nm Innovation
Synopsys partnered with TSMC to fast-track advanced-node System-on-Chip (SoC) designs on TSMC’s N2 process technology. Key highlights of the collaboration include certified design flows, powered by Synopsys.ai™ for improved productivity and IP portfolio development for HPC, AI, and mobile applications. AI-driven design optimization with Synopsys DSO.ai™ aims to enhance power efficiency, performance, and chip density.
“The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack,” said Sanjay Bali, vice president of strategy and product management for EDA at Synopsys. “This helps designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market.”
Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC, emphasized delivering high-quality results and faster time to market as the hallmarks of the longstanding collaboration between Synopsys and TSMC. This collaboration showcases Synopsys’ commitment to comprehensive EDA and IP solutions, supporting innovation and competitiveness. For example, below are some of the methodology innovations and Fusion Compiler innovations that are the results of Synopsys’ collaboration with TSMC. When moving from N3E to N2, power grid impacted routability ratio. Synopsys worked with TSMC to improve it and reduce the impact to less than 2% compared to N3E. Synopsys updated its clock tree synthesis methodology to be able to handle the wider clock library cells in N2. The company upgraded its Fusion Compiler tool to become vertically aware to accommodate N2’s multiple double height cells with different OD for scaling speed and power.
AI-Driven Analog Design Migration Flow for TSMC’s Advanced Process Technologies (N2, N3E, N4P and many others)
Synopsys expanded its analog design migration flow to cover TSMC’s advanced process technologies, including N4P, N3E, and N2. This flow, part of the Synopsys Custom Design Family, incorporates AI-driven circuit optimization, reducing manual effort and improving design quality. It includes interoperable process design kits (iPDKs) for TSMC FinFET nodes and an RF design reference flow for Radio Frequency Integrated Circuit (RFIC) designs. Sanjay Bali from Synopsys stressed the importance of AI-driven solutions in complex chip design and how customers can unlock massive productivity gains with efficient migration of their designs from node-to-node.
Dan Kochpatcharin from TSMC highlighted the significant performance and power efficiency advantages of TSMC’s advanced processes and the benefits of migrating existing analog designs to them.
Broadest Portfolio of Automotive-Grade IP on TSMC N5A Process
Synopsys has introduced a comprehensive portfolio of automotive-grade Interface and Foundation IP designed for TSMC’s N5A process. This IP is tailored to meet the demanding requirements of automotive System-on-Chip (SoCs) in terms of reliability and high-performance computing. It includes logic libraries, embedded memories, GPIOs, SLM PVT monitors, and PHYs for LPDDR5X/5/4X, PCIe 4.0/5.0, 10G USXGMII Ethernet, MIPI C-PHY/D-PHY and M-PHY, and USB. The portfolio adheres to the ISO 26262 standard for random hardware faults, facilitating the development of safety-critical SoCs for applications like advanced driver assistance systems (ADAS) and highly automated driving (HAD) systems.
“New generations of automotive SoC designs will need to support massive amounts of safety-critical data processed at extreme speeds and with high reliability,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys’ high-quality, automotive-grade Interface and Foundation IP on TSMC’s N5A process enables automotive OEMs, Tier 1s, and semiconductor companies to minimize IP integration risk and help meet the required functional safety, performance, and reliability levels for their SoCs.”
During a chat with John, he pointed to how electrification of automobiles is driving massive demand for automotive IP. And while EVs are just 15% of the market today, they are projected to make 2/3rds of the market by 2030. The OIP collaboration between Synopsys and TSMC supports this evolution of software-defined vehicles, enabling the processing of large volumes of safety-critical data with high reliability and performance.
Optimized Multi-Die System Design Solution for Higher Quality of Results
Synopsys has expanded its collaboration with TSMC to enhance multi-die system designs. It has introduced a solution supporting the 3Dblox 2.0 standard and TSMC’s 3DFabric™ technologies. Key elements include the unified exploration-to-signoff platform, 3DIC Compiler, which streamlines multi-die system design, and UCIe PHY IP, which achieved first-pass silicon success on TSMC’s N3E process, facilitating low-latency, low-power, high-bandwidth connectivity between dies. This collaboration addresses the challenges in high-performance computing, data center, and automotive applications, offering a comprehensive and scalable solution for optimized multi-die system designs.
“There’s a lot of work to be done to make multi-die systems a reality,” said Koeter. “Working closely with TSMC in many different areas is really key to executing and helping the industry to move to this new level of complexity.”
Accelerating RFIC Design with Reference Flow for TSMC N4PRF Process
Synopsys joined forces with Keysight Technologies and Ansys to introduce a new reference flow for TSMC N4PRF, a cutting-edge 4-nanometer (nm) radio frequency (RF) FinFET process technology. This collaboration addresses the growing complexity of RF integrated circuit design in next-gen wireless systems (WiFi-7 systems), which demand higher bandwidth, lower latency, and broader coverage. The reference flow, based on the Synopsys Custom Design Family, provides an open RF design environment with higher predictive accuracy and productivity. It integrates with Keysight’s RFIC design and electromagnetic analysis tools and incorporates Ansys’ EM modeling and signoff power integrity solutions. The outcome of this collaboration empowers RF designers to tackle the challenges of designing advanced RFICs for high-performance wireless systems.
The TSMC OIP Ecosystem Forum showcased the power of collaboration within the semiconductor ecosystem, with companies from various disciplines demonstrating their offerings leveraging TSMC’s technology. This article spotlighted the results from various collaborative efforts between Synopsys and TSMC as publicized through different news releases leading to the OIP Ecosystem Forum event. It is clear that Synopsys’ collaborative and development oriented investments and efforts are well aligned to its overarching Synopsys.ai and 3DIC initiatives to support futuristic electronic systems. And that in turn serves the TSMC OIP ecosystem well and helps unleash next-generation innovations.
To learn more, visit www.Synopsys.com.