The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs, where all components, such as the central processing unit (CPU), memory, and I/O interfaces, are integrated onto a single monolithic die. While this approach has served us well for many years, it has limitations in terms of scalability, power efficiency, and flexibility. This is where chiplets come into play.
Chiplets are smaller, modular semiconductor components that can be designed and manufactured independently. These chiplets can serve various functions, such as CPUs, GPUs, accelerators, memory controllers, and I/O interfaces. By breaking down the monolithic design into these smaller building blocks, chiplets offer several advantages. This concept of breaking down traditional monolithic computing architectures into chiplets leads to what is termed a disaggregated system. In addition to lower NRE, lower power and smaller die, disaggregated systems enable easier upgradability and scalability as per workload/application requirements. This approach also results in improved yield and cost efficiency and enhanced system performance and energy efficiency.
While chiplets-based designs bring several benefits, they also present a challenge, which is the issue of efficiently interconnecting these chiplets to create a cohesive computing system. The Universal Chiplet Interconnect Architecture (UCIe) addresses this challenge. UCIe is a standardized interconnect technology designed to provide high-speed, low-latency communication between chiplets and the motherboard. It serves as the glue that binds chiplets together, ensuring they can work seamlessly as a unified system. It enables energy efficiency, high bandwidth density, low end-to-end latency, and robustness.
Disaggregated systems enable data center operators to tailor their computing resources to specific workloads, improving resource utilization and energy efficiency. This is especially valuable in cloud computing environments. High performance computing clusters can benefit from the flexibility of chiplets, allowing for specialized accelerators to be added or replaced as needed, maximizing computational power. In edge computing deployments, where space and power constraints are significant, disaggregated systems can be customized for specific edge applications, such as AI inference or data processing.
At the Recent TSMC Open Innovation Platform (OIP) Ecosystem Forum
At the most recent TSMC OIP Ecosystem Forum, there were many interesting presentations from various ecosystem partners. One presentation that covered the topic of disaggregated systems was from Letizia Giuliano of Alphawave Semi.
UCIe Complete Solution from Alphawave Semi
At the physical layer, the solution includes an Electrical PHY (AFE) that leverages silicon-proven analog IP. This component handles essential functions like clocking, link training, and sideband signals. Additionally, it incorporates a Logical PHY with Multi-Module PHY logic, providing a top-level floorplan for flexible package options.
The UCIe Die-to-Die (D2D) Adapter ensures smooth D2D interconnectivity. It manages link state, negotiates parameters crucial for chiplet interoperability, and ensures a reliable link by implementing CRC and link-level retry mechanisms. At the protocol layer, the solution natively maps PCIe and CXL protocols via Flit-Aware Mode and offers a Streaming Protocol Bridge for diverse SoC interfaces. Furthermore, Alphawave Semi provides a comprehensive platform for electrical, physical form factor, and protocol compliance, along with a complete set of test vehicles to facilitate interoperability testing.
Together, the above components enable a robust and complete UCIe solution, addressing various aspects of die-to-die chiplet integration and ensuring seamless functionality support for disaggregated systems.
Chiplets have emerged as a game-changer in the world of System-on-Chip (SoC) design, especially within advanced manufacturing nodes. Compared to traditional technologies, chiplets offer significant advantages, allowing for diverse SoC design structures. A robust and open chiplet ecosystem relies on Interface IPs and the UCIe Die-to-Die (D2D) standard is fostering such an open ecosystem. It facilitates seamless communication between chiplets from different manufacturers, ensuring compatibility and interoperability. Additionally, the integration of higher-level packaging takes chiplets to a new level, offering a wide range of utilization scenarios.
As a forward-thinking industry player, Alphawave Semi provides comprehensive D2D IP Subsystem Solutions, application optimized Chiplet Architectures and complete custom silicon solutions on leading edge nodes down to 3nm, to meet the needs of future System-in-Packages (SiPs). As a long-standing partner of TSMC in the Open Innovation Platform®, Alphawave Semi is very active in TSMC’s IP Alliance, Virtual Channel Aggregator (VCA), Design Center Alliance (DCA) and the new 3DFabricTM Alliance.