On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide custom silicon that are optimized per application. The company recently announced a 3nm tape-out on July 10th to prove out chiplets for generative AI applications that use a High Bandwidth Memory 3 (HBM3) PHY and Universal Chiplet Interconnect Express (UCIe) PHY IPs. The UCIe PHY IP supports die-to-die data rates of 24Gbps per lane. There’s been tremendous interest with custom silicon and chiplets, caused by the data explosion from using LLM and ChatGPT applications that require fast connectivity rates.
All of that data generated getting into and out of chiplets requires high-speed, low-power, data connectivity. There have been a couple of chiplet interconnect approaches, with Buch Of Wires (BOW) and UCIe as the two most predominant, and UCIe being more standardized for chiplets. BOW was there at the start in 2020 as a die-to-die interface.
Praveen Vaidyathan, VP at Micron noted that, “The tape-out of Alphawave Semi’s HBM3 solution in TSMC’s most advanced 3nm process is an exciting new milestone. It allows cloud service providers to leverage Alphawave Semi’s HBM3 IP subsystems and custom silicon capabilities to accelerate AI workloads in next-generation data center infrastructure.”
At DAC they were demonstrating four things:
- 3nm 112GB s XLR, PAM4 SERDES
- PCIe Gen 6 with PAM 4
On the demo of 112GB Ethernet they were showing their test chip using a loop back test, and the longer length interconnect creates more delays as they wanted to max out the simulated length. A Bit Error Rate (BER) of 2e-8 was measured, while the actual spec is 1e-4, so their results are 4 orders magnitude ahead of the spec. That BER number can even be brought down to 1e-10. The PAM4 eye diagram was prominently displayed in the demo. The test chip is multi-standard, so Ethernet or PCIe are both supported for all generations. Four lanes are possible, although only one was being shown in the demo.
TSMC was the foundry for the 3nm test chip and Alphawave Semi used a DSP-based SerDes, and has a rich history of SerDes IP, where there has been sufficient margins designed in. The PCIe 7.0 specification requires 128 GT/s raw bit rate, but the final spec is targeted for release in 2025.
Generative AI system designs require a complete IP subsystem with connectivity for chiplets, custom silicon and advanced packaging. This is all coming together in the industry now.
Alphawave Semi has about 700 people worldwide now, and just one year ago it was 400 people, so that’s a lot of growth, fueled by connectivity IP demand. The company has sites in Canada, USA, UK, Israel, India, China, Taiwan and South Korea.
The 3nm demo from Alphawave Semi at DAC was pretty impressive, and the 112G PAM4 eye diagram looked open and clean. Most of DAC is filled with EDA vendors, but it’s always refreshing to witness real silicon IP operating in a booth.
- Coherent Optics: Synergistic for Telecom, DCI and Inter-Satellite Networks
- Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
- Alphawave Semi at the Chiplet Summit
- Alphawave IP is now Alphawave Semi for a very good reason!
- High-End Interconnect IP Forecast 2022 to 2026
- Integration Methodology of High-End SerDes IP into FPGAs
- Die-to-Die IP enabling the path to the future of Chiplets Ecosystem
- Webinar – 112 Gbps PAM4 Implementation with Real-World Case Studies