IBM has announced the development of a 2nm process.
What was announced:
- 50 billion transistors in a “thumbnail” sized area later disclosed to be 150mm2 = 333 million transistors per millimeter (MTx/mm2).
- 44nm Contacted Poly Pitch (CPP) with 12nm gate length.
- Gate All Around (GAA), there are several ways
… Read More
TSMC recently announced plans to spend $100 billion dollars over three years on capital. For 2021 they announced $30B in total capital with 80% on advanced nodes (7nm and smaller), 10% on packaging and masks and 10% on “specialty”.
If we take a guess at the capital for each year, we can project something like $30B for 2021 (announced),… Read More
In January I presented at the ISS conference a comparison of Intel’s, Samsung’s and TSMC’s leading edge offerings. You can read a write-up of my presentation here.
With the problems going on at Intel, that article generated a lot of interest in the investment community, and I have been holding a lot of calls with analysts who are trying… Read More
At the SPIE Advanced Lithography Conference held in February, ASML presented the latest information on their Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) exposure systems. I recently got to interview Mike Lercel of ASML to discuss the presentations.
Despite all the attention EUV is getting, most layers are still… Read More
There are reports in the media that TSMC is now planning six Fabs in Arizona (the image above is Fab 18 in Taiwan). The original post I saw referred to a Megafab and claimed six fabs with 100,000 wafers per month of capacity (wpm) for $35 billion dollars. The report further claimed it would be larger than TSMC fabs in Taiwan.
This report… Read More
There is a lot of interest right now in how Intel compares to the leading foundries and what the future may hold.
Several years ago, I published several extremely popular articles converting processes from various companies to “Equivalent Nodes” (EN). Nodes were at one time based on actual physical features of processes but had… Read More
I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk.
The title of the talk is “Logic Leadership in the PPAC era”.
The talk is broken up into three main sections:
- Background information explaining PPAC and Standard Cells.
- A node-by-node comparisons of companies running leading edge logic
… Read More
As I have discussed before, I believe that IEDM is the premier technical conference for understanding leading edge process technologies. Beginning this coming weekend, this year’s edition of IEDM will be held virtually, and I highly recommend attending.
The conference held a press briefing last Monday. The tutorial and short… Read More
Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More
The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.
It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More