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Talking Directly to EDA R&D

Talking Directly to EDA R&D
by Daniel Payne on 08-02-2015 at 12:00 pm

Many EDA companies keep their R&D engineers focused on product development and bug fixing, shielding them from any and all direct contact with end-users, mostly for fear of what might be revealed if such direct dialog were allowed. Customer support people are allowed to talk directly with customers, then pass along enhancement requests or file bug reports to R&D. Another way is for product marketing and technical marketing folks to talk with EDA users and uncover new product requirements, then report to R&D what they’ve heard about possible roadmap features. Direct conversations between EDA tool users and EDA R&D engineers is kind of rare, however it can be quite beneficial to both parties as there is no intermediate filtering of ideas, design challenges, likes and dislikes.

I was actually kind of surprised to learn that Dassault Systemes is having a two day user meeting in September and October where the second day is fully dedicated to EDA users talking directly with EDA R&D engineers to actually share their user experience, have roundtable discussions, discuss product roadmaps, describe how they actually use the tools, and explain what they really want to see in the next release of software. This kind of direct interaction between users and developers is a wonderful approach that keeps a company like Dassault in tune with what’s really happening, and able to plan and respond accordingly.

Related – A Systems Company Update from #52DAC

As a quick recap, Dassault has introduced the Silicon Thinking Experience which offers four solution areas for SoC design teams that provide a business platform allowing Design, Product and Manufacturing engineering to work together:

  • Design Collaboration using DesignSync and Pinpoint
  • Requirements driven verification
  • Enterprise-level IP management
  • Manufacturing Collaboration

DesignSync has been used since 1998 to help SoC teams manage both the hardware and software content in their electronic products. Designers can share their hierarchical design to all team members, even across the globe during their collaboration of design and verification.

The Pinpoint tool came from Tuscany Design Automation, and was acquired by Dassault in late 2012, it provides a dashboard with info for both the front-end and back-end IC design flows, helping you to reach design closure quicker.

Knowing if your system design implementation actually meets the original requirements is important for success, so having a methodology that supports requirements driven verification is essential. Ad-hoc verification just isn’t sufficient for a complex electronic product today.

How you manage the hundreds of IP blocks on a single SoC can be a critical success factor, so using a proven system will help reduce risks, enable IP reuse, eliminate duplication of IP and track issues and defects through multiple projects.

Related – Design Collaboration, Requirements and IP Management at #52DAC

Agenda
Here’s a snapshot of the first day activities, open to anyone interested in learning about the Silicon Thinking Solution Experience:

[TABLE] border=”1″ style=”width: 545px”
|-
| style=”width: 48px; height: 20px” | Start
| style=”width: 53px; height: 20px” | End
| style=”width: 61px; height: 20px” | Length
| style=”width: 384px; height: 20px” | ENOVIA Semiconductor Connection User Day
|-
| style=”width: 48px; height: 20px” | 8:30
| style=”width: 53px; height: 20px” | 9:00
| style=”width: 61px; height: 20px” | 0:30
| style=”width: 384px; height: 20px” | Check-in
|-
| style=”width: 48px; height: 20px” | 9:00
| style=”width: 53px; height: 20px” | 9:10
| style=”width: 61px; height: 20px” | 0:10
| style=”width: 384px; height: 20px” | Introduction by Dassault Systèmes
|-
| style=”width: 48px; height: 20px” | 9:10
| style=”width: 53px; height: 20px” | 10:00
| style=”width: 61px; height: 20px” | 0:20
| style=”width: 384px; height: 20px” | Shaping Semiconductor Design and Manufacturing
|-
| style=”width: 48px; height: 20px” | 10:00
| style=”width: 53px; height: 20px” | 10:30
| style=”width: 61px; height: 20px” | 0:30
| style=”width: 384px; height: 20px” | Modern SoC Design –
Assembling the Right Pieces Part 1:
Streamlined SoC Design Closure
|-
| style=”width: 48px; height: 20px” | 10:30
| style=”width: 53px; height: 20px” | 10:45
| style=”width: 61px; height: 20px” | 0:15
| style=”width: 384px; height: 20px” | Break – Coffee
|-
| style=”width: 48px; height: 26px” | 10:45
| style=”width: 53px; height: 26px” | 11:45
| style=”width: 61px; height: 26px” | 1:00
| style=”width: 384px; height: 26px” | Modern SoC Design –
Assembling the Right Pieces Part 2:
Effective SoC Design Collaborations
|-
| style=”width: 48px; height: 20px” | 11:45
| style=”width: 53px; height: 20px” | 12:15
| style=”width: 61px; height: 20px” | 0:30
| style=”width: 384px; height: 20px” | Tying Verification and Validation to System Requirements
|-
| style=”width: 48px; height: 20px” | 12:15
| style=”width: 53px; height: 20px” | 13:30
| style=”width: 61px; height: 20px” | 1:15
| style=”width: 384px; height: 20px” | Networking Lunch
|-
| style=”width: 48px; height: 20px” | 13:30
| style=”width: 53px; height: 20px” | 14:30
| style=”width: 61px; height: 20px” | 1:00
| style=”width: 384px; height: 20px” | Linking Design and Manufacturing for the First Time
Back Annotate Yield and Volume Into Design
|-
| style=”width: 48px; height: 14px” | 14:30
| style=”width: 53px; height: 14px” | 14:45
| style=”width: 61px; height: 14px” | 0:15
| style=”width: 384px; height: 14px” | Break – Coffee
|-
| style=”width: 48px; height: 20px” | 14:45
| style=”width: 53px; height: 20px” | 16:00
| style=”width: 61px; height: 20px” | 1:15
| style=”width: 384px; height: 20px” | Achieving Greater Predictability and Repeatability
How to Reduce Re-Spins
|-
| style=”width: 48px; height: 20px” | 16:00
| style=”width: 53px; height: 20px” | 16:15
| style=”width: 61px; height: 20px” | 0:15
| style=”width: 384px; height: 20px” | Day 1 Wrap up and Closing Remarks
|-

Related – Managing Semiconductor IP

The second day connects existing users of the Dassault solutions with Dassault’s R&D engineers:

[TABLE] border=”1″ style=”width: 545px”
|-
| style=”width: 48px; height: 21px” | Start
| style=”width: 53px; height: 21px” | End
| style=”width: 61px; height: 21px” | Length
| style=”width: 384px; height: 21px” | ENOVIA Semiconductor Solution Education Day
|-
| style=”width: 48px; height: 21px” | 8:30
| style=”width: 53px; height: 21px” | 9:00
| style=”width: 61px; height: 21px” | 0:30
| style=”width: 384px; height: 21px” | Check in
|-
| style=”width: 48px; height: 21px” | 9:00
| style=”width: 53px; height: 21px” | 9:05
| style=”width: 61px; height: 21px” | 0:05
| style=”width: 384px; height: 21px” | Introductions
|-
| style=”width: 48px; height: 21px” | 9:05
| style=”width: 53px; height: 21px” | 9:15
| style=”width: 61px; height: 21px” | 0:10
| style=”width: 384px; height: 21px” | Welcome
|-
| style=”width: 48px; height: 21px” | 9:15
| style=”width: 53px; height: 21px” | 9:45
| style=”width: 61px; height: 21px” | 0:30
| style=”width: 384px; height: 21px” | ENOVIA Semiconductor Solutions – Overview and What’s New
|-
| style=”width: 48px; height: 21px” | 9:45
| style=”width: 53px; height: 21px” | 10:45
| style=”width: 61px; height: 21px” | 1:00
| style=”width: 384px; height: 21px” | Customer Experience Presentations
|-
| style=”width: 48px; height: 21px” | 10:45
| style=”width: 53px; height: 21px” | 12:00
| style=”width: 61px; height: 21px” | 1:15
| style=”width: 384px; height: 21px” | R&D Roundtable: Roadmap Discussions
|-
| style=”width: 48px; height: 21px” | 12:00
| style=”width: 53px; height: 21px” | 1:00
| style=”width: 61px; height: 21px” | 1:00
| style=”width: 384px; height: 21px” | Networking Lunch
|-
| style=”width: 48px; height: 21px” | 13:00
| style=”width: 53px; height: 21px” | 15:30
| style=”width: 61px; height: 21px” | 2:30
| style=”width: 384px; height: 21px” | R&D Working Session – User Driven Discussion:
· Discuss Current Use Models & Product
· Document Customer Inputs, Requirements
|-
| style=”width: 48px; height: 21px” | 15:30
| style=”width: 53px; height: 21px” | 15:45
| style=”width: 61px; height: 21px” | 0:15
| style=”width: 384px; height: 21px” | Break – Coffee
|-
| style=”width: 48px; height: 21px” | 15:45
| style=”width: 53px; height: 21px” | 16:45
| style=”width: 61px; height: 21px” | 1:00
| style=”width: 384px; height: 21px” | Requirements Feedback – Presentation to R&D
|-
| style=”width: 48px; height: 21px” | 16:45
| style=”width: 53px; height: 21px” | 17:00
| style=”width: 61px; height: 21px” | 0:15
| style=”width: 384px; height: 21px” | Next Steps and Closing Remarks
|-


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