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Assertion Synthesis: Atrenta, Cadence and AMD Tell All

Assertion Synthesis: Atrenta, Cadence and AMD Tell All
by Paul McLellan on 02-11-2013 at 6:22 pm

Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta’s BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the product.

Creating an adequate number of high quality assertions and coverage properties is a challenge in any verification plan. Assertion Synthesis takes as input the RTL description of the design and its test environment and automatically generates high quality whitebox assertions and coverage properties in standard language formats such as SVA, PSL and Verilog. Assertion Synthesis enables an automated assertion-based verification methodology that improves design quality and reduces verification overhead.

 Here’s the 5000ft version of what Assertion Synthesis is. BugScope watches the simulation (or emulation, which I think of as a special sort of simulation) of the design and observes its behavior. Based on what it sees, BugScope automatically generates syntactically correct assertions about the design, behaviors that it believes are always true based on the simulation.

The designer and verification engineers can use these assertions in three different ways:

[LIST=1]

  • They agree with BugScope that the assertion should always be true. There is now a new assertion that can be used in subsequent verification runs that is ready for use. Construction of syntactically correct assertions can take hours so this is a real time saver. Of course, once included in the verification run, the assertion will trigger anytime the condition is violated making it easy to track down the newly introduced problem.
  • The assertion should not always be true. But this means that there are not enough simulation vectors to exhibit to BugScope any situation in which it is actually not true. This is a real coverage hole and more vectors are required. This is obviously also very useful information.
  • The assertion is indicating a behavior that should, in fact, never happen. BugScope has identified a real design issue, something it considers should happen that the designer knows should not.

    All three of these alternatives result in an improved verification process: either more assertions added very cheaply, a coverage hole identified, or a real error in the design.

    The DVCon tutorial, which is officially titled Achieving Visibility into the Functional Verification Process using Assertion Synthesis, is on Thursday February 28th from 1.30pm to 5pm in the Donner Ballroom. More details are here.

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