IC Test Debug at Altera

My background is IC design engineering, so it’s always a delight to talk with another engineer on their chip challenges. Today I spoke by phone with Sucharita Biswas, a Senior Hardware Engineer at Altera involved in IC test debug for FPGA devices.

Q: What is your IC design and test background?
A: I’m a test engineer at Altera, and also worked at Sun Microsystems. I have a Masters in EE and have done memory BIST (Built In Self Test) and logic BIST. I work on testability aspects of new products, checking out the silicon.

Altera Stratix IV wafer, 40nm process

Q: What types of tests are you writing?
A: I have been working on PLL testing, distributed memory testing, and the core IP. Other groups test the IOs.

Q: What are you testing for?
A: Several things: stuck-at faults, transition faults, and path delays. The strategy is to use DFT approaches, and structural test with functional vectors.

Q: What type of EDA tools are used in your job for test debugging?
A: We discovered the StarVision Protool from Concept Engineering and have been using it to help us view the design, and verify our DFT approaches. We have mixed netlists with RTL, gate and transistor-level. With StarVision we can view the entire design, then come up with a test approach that makes sense.

It has a cone view, so that we traverse the design and see the cone of logic expand.

We work across geographies with a team in Penang, and they can quickly pick up where we end off each day.

We can look at our simulation results and look at the generated schematic with annotated simulation values, which is helpful to uncover the source of X’s for example. This helps shorten our turn-around time for debug issues, so that in 10 minutes I can look at waveforms and look at the generated schematic, find and fix the testability issue. It’s really saving us days of time with this new visual debug approach per test issue.

We’ve even automated a way to get logic cones in batch mode, instead of interactive, saving more time on debug.

Q: How did you hear about the StarVision tool?
A: On a previous project I had seen the StarVision tool, and decided to use it on my DFT projects to save us debug time. There are about 25 test engineers using StarVision now, and once they use it to understand a new design it really helps in DFT debug.

Even with a new and incomplete design with partial RTL, gates and transistors we can still start looking at a new design and understand how to start writing test programs. We can start doing DFT work in parallel with the design group, which shortens our time to market.

Q: For RTL simulation, what tool are you using?
A: We use the Synopsys VCS simulator for RTL simulation work.

Q: Are you doing any gate-level or transistor-level simulations?
A: We’re moving away from that level of simulation, and prefer instead to use RTL simulation and equivalency checking instead.

Q: How about ATPG tools?
A: We’re using TetraMax from Synopsys.

As the production volume ramps up, then the test program run times get shorter. At first we are doing much debug.

Summary
Test engineers at Altera use a variety of EDA tools to aid in their debug process, and the StarVision Pro tool from Concept Engineering helps them shorten the test debug time by providing an auto-generated schematic at the RTL, gate and transistor levels which can cross-probe with simulation results to pinpoint error sources.

Further Reading

• Visually Debugging IC Designs for AMS and Mixed-Languages
• Visual Debugging at Altera on Billion-Transistor Chips

Webinar

• Circuit Analysis & Debugging: Fast and Easy !, April 9th, 10AM PDT