Visually Debugging IC Designs for AMS and Mixed-Languages

With an HDL-based design methodology many IC engineers code in text languages like SystemVerilog and VHDL, so it’s only natural to use a text-based debug methodology. The expression that, “A picture is worth a thousand words” comes to my mind and in this case a visual debug approach is worth considering for AMS and mixed-language IC designs.

Let’s say that on your SoC project there are multiple IP blocks being re-used, and that they are coming from another design group, another design location, or even another company. How would you get up to speed in understanding not only the interconnects to the IP block, but also take a peek inside the IP to best understand the structure or behavior?

It would take way too long to directly read the text in SystemVerilog or VHDL, then create a graphical representation manually. You have better things to do with your engineering talent then manually visualize how an IP block was designed. The good news is that there is EDA technology available that can:

Read in a mixed-language netlist

• SystemVerilog
• VHDL

Read in a gate-level netlist

• EDIF

Read in a transistor-level netlist

• SPICE
• HSPICE
• Eldo

Read in interconnect netlist

• DSPF

This EDA technology is called StarVision PROand is developed by a German-based company called Concept Engineering. I first met the President and CEO, Gerhardt Angst, several years ago when I worked at Mentor Graphics and we needed a way to visualize SPICE and DSPF netlists that were supplied by FastSPICE users.

We used SpiceVision PRO and it was the only automated method that we could find that would quickly and accurately create a SPICE netlist, on the fly, with very little learning curve. It was a real time-saver for us, because we could quickly visualize the unknown circuits being simulated at the transistor level, traverse the hierarchy, and understand more of the design intent of the netlist. The transistor-level netlists were easy to read, and the logic flowed naturally from left to right, as neatly as if someone had hand-drawn the schematics.

Gerhard Angst, Concept Engineering

Webinar
If you are debugging IP at the RTL, gate, transistor or interconnect levels, and want to save some time in that process, then plan to attend their webinar next week on Tuesday, March 12th, 10:00AM PDT. Registration is online, and will fill up fast, so attend and get your questions answered about how a visual debug approach will save you time and effort.