We agree now that FD-SOI technology is Faster, Cooler, Simpler. But can it also be a cheaper technology? Let start with an overview of the current estimation of the development cost for complex SoC on advanced technology nodes. The following data are extracted from International Business Strategies, Inc 2013 report. The first picture shows the Hardware Design Cost evolution in respect with the target design node. The exponential nature of the growth rate is known for a couple of years at least, I think it’s good to remind these data points:
- 28nm H/W Design cost is: $50M
- 20nm H/W Design cost is: $95M
- 16/14nm H/W Design cost jump to $193M
Because a chip maker will have to integrate these development cost into the Integrated Circuit (IC) selling price, it should target a market large enough to sell several dozen million IC, if not hundred million. And this chip maker should target a technology offering the cheapest cost per gate data point.
The next picture will not make life easier for this chip maker: the cost per gate trend is reversed from 20nm node! Because the market targeted by this chip maker is certainly ultra-competitive (remember, it’s a several hundred million chip segment, attracting many players), every chip generation is expected to integrate more features, and more functions (CPU, GPU, SRAM, DSP etc.), moving to the next technology is not a choice, it’s a requirement.
The above picture is based on Bulk Silicon technology, so what can be the cost of FD-SOI technology in comparison? Thanks to an active Semiwiki reader, Scott W Jones, who has posted a relevant comment on a previous blog, and direct me to: FDSOI more cost effective than bulk for 22nm SOC I have extracted the following table, which is a cost comparison between a 20nm Bulk fabricated wafer cost, and a 22nm FD-SOI. This table will provide us with the 20nm data point:
You may want to read the complete article to check the methodology used to come to this table (just click on the title above), the very interesting point is that both cost are within 1 or 2 %. The starting wafer cost (material) at $500 for FD-SOI instead of $130 for Bulk is compensated: FD-SOI is simpler, this means that there are less masks and less technology steps, less equipment (depreciation and maintenance), lower labor cost… And, by the way, the lead time to process FD-SOI wafer is shorter! If you have ever waited for ASIC prototypes to come back to the wafer fab, I am sure you will greatly appreciate this benefit! And the chip maker marketing team will also appreciate to benefit from such a shorter lead-time during production ramp-up, to accelerate TTM.
So far, I did not use any data coming from ST-Microelectronics, FD-SOI champion, along with IBM and GlobalFoundries, but after searching the web, I could not find data to be used to generate other data points, at 28nm and 14 (or 16)nm. This table was presented during IP-SoC 2013 in Grenoble, so I have downloaded the slides (here) from STM keynotes presentation to have enough time to carefully look at it:
If we look at the first cell in the table, 28nm planar FD-SOI vs 28nm HKMG bulk planar, we just see “FD-SOI showing better cost”. In the worst case, we can say that FD-SOI is cheaper or at the same cost than HKMG bulk planar technology, assuming the fabrication related cost could be very similar to the cost listed in the previous table. In fact, digging in the presentation, we can find this picture.
The outcome is:
- 28nm FD-SOI is the same cost than 28LP
- 28nm FD-SOI provides the same performances as 28G…but a 15% lower cost.
Thus, we have the next data point: FD-SOI is cheaper by 10-15% than 28G bulk planar technology, at equivalent performance. Another data point would be interesting: the comparison between 14/16 planar FDSOI and 14/16 bulk FinFet. According with the above (Benefits) Table, 14nm Planar FD-SOI Fabricated wafers are 35% cheaper than 14nm FinFet Bulk. That makes sense, as the SOI wafer over-cost ($500 vs $130) is certainly more than compensated by the numerous extra process steps needed to create the 3D FinFet structure… It would be good to benefit from cost data point coming from an independent source, as far as I know, some current research is on-going, so I will update this article as soon as such data will be available.
Let me quote Pr Asen Asenov, Professor at The University of Glasgow (and CEO of Gold Standard Simulations (GSS) Ltd), who has run some very interesting research on the topic: “Making SOI finfets is cheaper than bulk finfets, but SOI wafers are more expensive, so if a foundry goes to SOI it has to give some of its profits to the SOI manufacturer. So bulk is better for foundries and that’s why they’re going for bulk at 16nm and 14nmm. But SOI has the advantage. For foundries it’s not the most important thing to have the best technical solution but to have the solution which produces the most revenue.” Clearly, Pr Asenov considers that SOI (FinFet or even more Planar) technology is cheaper than Bulk FinFet. He is also making a very good point when noting that a higher part of the fabricated wafer margin is going to raw SOI wafers vendor, explaining why foundries prefer to use Bulk technology: they can keep a higher part of the overall margin when selling Bulk wafers…
Faster, Simpler, Cooler,…and Cheaper: FD-SOI technology should get very good traction in the near future!
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