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Cadence CEO Keynotes DVCON 2014!

Cadence CEO Keynotes DVCON 2014!
by Daniel Nenni on 12-10-2013 at 8:00 pm


Next year’s DVCon attendees can expect to learn about both practical solutions to their pressing problems that can be applied today and also receive a preview of the technologies that will affect them in the near future. DVCON is March 3-6, 2014 @ the DoubleTree Hotel in San Jose.

KEYNOTE: An Executive View of Trends and Technologies in Electronics

The Semiconductor Revolution continues to drive tremendous economic growth more than 50 years after it began. Today’s major trends – like cloud computing, wearable computing, and the internet of things – are fueled by innovations in product design using advanced semiconductors.

But rapid market trends bring increasing time-to-market pressures that threaten to stifle innovation. The technical challenges of SoC design for advanced process nodes, as well as system issues like communications performance, data security, and ultra-low-power design, create increased complexity and risk. From a business standpoint, the cost of developing the software is becoming the biggest factor in SoC design, followed by the cost of verifying everything – including the software.

One of the ways the electronics industry addresses these challenges is through improvements in design technology. The EDA industry, including Cadence, is investing billions of dollars to develop new design technologies and methodologies to keep the semiconductor industry moving forward. In this keynote, Lip-Bu Tan will discuss the relationships between market trends, opportunities, and challenges, and show how new design technologies are an essential element of continuing innovation.

Lip-Bu Tan has served as President and CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. He also serves as chairman of Walden International, a venture capital firm he founded in 1987.

PANELS @ DVcon:

Is Software the Missing Piece In Verification?
Panelists from different segments of the semiconductor industry will discuss and debate the presumed need, maturity, scalability, and adoptability of software-driven system-level verification tools, as well as what’s needed to get them to mass usability level. In addition, panelists will discuss current approaches to the verification problem and what place this technology has with respect to current verification methodologies such as UVM.
See the exciting line-up of panelists.

Did We Create the Verification Gap?
Panelists will explore how verification teams interact with broader project teams and examine the characteristics of a typical verification effort, including the wall between design and verification, verification involvement (or lack thereof) in the design and architecture phase, and reliance on constrained random in absence of robust planning and prioritization to determine the reasons behind today’s Verification Gap.
More details.

TECHNICAL SESSIONS @ DVcon:

  • System-Level Design
  • Formal and Semi-Formal Techniques
  • Hw/Sw Co-Verification
  • Advance Methodologies and Testbenches
  • Mixed-Signal Design and Verification
  • Low Power Design & Verification
  • Automated Stimulus Generation
  • SoC and IP Integration Methods and Tools
  • Interoperability of Models and/or Tools

REGISTER NOW

DVCon is the premier conference for the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The primary focus of DVCon is on the practical use of specialized design and verification languages such as SystemC, SystemVerilog and e, assertions in SVA or PSL, as well as the use of AMS languages, design automation using IP-XACT and the use of general purpose languages C and C++.
Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools.

lang: en_US

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