WP_Term Object
    [term_id] => 72
    [name] => STMicroelectronics
    [slug] => stmicroelectronics
    [term_group] => 0
    [term_taxonomy_id] => 72
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 77
    [filter] => raw
    [cat_ID] => 72
    [category_count] => 77
    [category_description] => 
    [cat_name] => STMicroelectronics
    [category_nicename] => stmicroelectronics
    [category_parent] => 14433

FD-SOI the Synapse Way

FD-SOI the Synapse Way
by Paul McLellan on 05-18-2015 at 7:00 am

 Last week I talked to Marco Brambilla of Synapse Design. Synapse is a design services company headquartered in Silicon Valley. It was founded in 2003 by Satish Bagalkotkar and has been profitable since the beginning. Today it has over 700 people. In addition to the headquarters in Santa Clara, they have a software group in Colorado, and design centers in Shanghai, Bangalore, Taiwan, Italy and more. They are a pure design services company. While most of their projects are some version of ASIC, Synapse engagement models also include customer-provided RTL and Synapse completes the design tapeout, or a full turnkey starting from architecture or specification down to design tapeout.

As you might guess from his name, Marco is Italian. But he works in Santa Clara today, having relocated to the US from one of Synapse’s European sites in Grenoble. Prior to that he worked for ST Microelectronics for a decade in both the US and Italy (and short stays in several other countries). Marco is a director of engineering at Synapse but he is also their resident expert on FD-SOI design, given his long history at ST.

In 2012 Synapse worked on a mobile chip and he thinks that this is the first FD-SOI production ASIC. They worked closely with ST since they were blazing a trail and helping to mature the design flows. Since then they have taped out another 3 or 4 chips that are in production, in both mobile and networking. All these chips involve aggressive power management with multiple power domains and all the tricks that used to be esoteric and are now mainstream.
 One of the things that FD-SOI brings that is not available in FinFET is the capability to back-bias which can be used in a number of different ways, either to increase performance or to reduce power (especially leakage). I asked Marco if they had used it. He said that on the first modem chip they had indeed used it in order to get the performance up, but they had not used it on the networking chips. It is not yet a mature technology and use requires significant involvement of the foundry (today ST and Samsung have announced availability).

Currently Synapse are close to taping out a chip for a machine-to-machine communication (IoT) device. A portion of the chip is always-on. The rest of the chip spends a lot of its time powered down with just retention registers holding values for when everything gets reactivated. They even include an embedded PCM (process control monitor) to really measure accurately the PVT conditions during use. Their plan of record is to use back-biasing to keep leakage very low and they are in discussions with ST about the details. The usage of back-biasing is not yet completely turnkey. The effect for the designer is largely that it removes the slow corner and adds a few more timing corners that need to be checked. But there are already lots of timing corners at 28nm and below, so this is not a lot of extra work. However, once a back-biased design goes into production, a few samples are required and then tuning needs to be done to calibrate exactly how the product behaves. This is especially important when using DVFS (dynamic voltage and frequency scaling). One big challenge is making the biasing temperature independent, something that is a challenge with DVFS no matter what technology is in use.

I asked Marco what was the sweet spot for FD-SOI. Obviously Synapse does designs in lots of other processes including FinFET. He said that the sweet spot is non-extreme-high-performance, not humungous gate counts, where power control is important (is it ever not?). Not the 300-400M gates, but rather the 10-20mm square devices. For consumer devices the mask cost and wafer cost goes down predictably from being a 28nm planar process. It has the buried box but it does not need the masks and process steps for the stress relief used in bulk technologies.

Another advantage is the comparatively wide operating voltage range. On the current chip they started assuming they would use a 40nm low power process and when Marco started talking about 28nm FD-SOI, everyone thought he was crazy. But a small device has very good yields. And whereas at 40LP every foundry only has 1.1V on 28nm FD-SOI can run from 0.8V up to 1.1V. With care in memory choice (or splitting the core from the periphery) the voltage can be reduced even further to 0.65V with obvious savings in power.

There is a perception that ST is a small fab but with Samsung as a partner that is not an issue. Marco told me that they have several customers with active FD-SOI projects and not just with ST.

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.