Next-Generation Formal Verification

Next-Generation Formal Verification
by Daniel Nenni on 12-14-2018 at 12:00 pm

As SoC and IP designs continue to increase in complexity while schedules accelerate, verification teams are looking for methodologies to improve design confidence more quickly. Formal verification techniques provide one route to improved design confidence, and the increase in papers and interest at industry conferences… Read More


Si Photonics in a 300mm Fab – This is Getting Serious!

Si Photonics in a 300mm Fab – This is Getting Serious!
by Mitch Heins on 05-13-2016 at 7:00 am

Image RemovedGreater demand for more data exchange within data centers is being driven by mobile computing and the Internet-of-Everything. In 2011, it was estimated that over 1 Zettabytes (ZB) of data was pushed through the internet. That’s 1×10[SUP]21[/SUP] bytes of data. And, that amount has been doubling every 3 years… Read More


Thomas Skotnicki: FD-SOI 26 Years in the Making

Thomas Skotnicki: FD-SOI 26 Years in the Making
by Paul McLellan on 07-23-2015 at 7:00 am

Image RemovedIt seems to be FD-SOI week yet again. I talked to Thomas Skotnicki this morning. He is the father of thin-box FD-SOI and its birth is an interesting story. The story began 26 years ago (so not quite as far back as the photo!).

Thomas is of Polish origins (he is actually Tomeczek) and grew up in Warsaw where he earned his PhD.… Read More


High Level Synthesis. Are We There Yet?

High Level Synthesis. Are We There Yet?
by Paul McLellan on 06-16-2015 at 7:00 am

Image RemovedHigh level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the… Read More


FD-SOI the Synapse Way

FD-SOI the Synapse Way
by Paul McLellan on 05-18-2015 at 7:00 am

Image RemovedLast week I talked to Marco Brambilla of Synapse Design. Synapse is a design services company headquartered in Silicon Valley. It was founded in 2003 by Satish Bagalkotkar and has been profitable since the beginning. Today it has over 700 people. In addition to the headquarters in Santa Clara, they have a software … Read More


Grenoble Comes to San Francisco

Grenoble Comes to San Francisco
by Paul McLellan on 04-14-2015 at 7:00 am

Image RemovedThe headquarters of ST Microelectronics is officially in Switzerland, but in many ways the center of gravity is in the Grenoble area. You may have heard of Crolles where ST does process development, manufacturing and more, which is about ten miles north-east of the city. As a result, along with the CEA-LETI and Grenoble… Read More


FD-SOI Foundry

FD-SOI Foundry
by Paul McLellan on 03-16-2015 at 7:00 am

Image RemovedAt the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the… Read More


FD-SOI at Samsung

FD-SOI at Samsung
by Paul McLellan on 02-08-2015 at 7:00 am

Image RemovedVarious foundries have made announcements about licensing FD-SOI technology from ST Microelectronics and then fallen quiet. GlobalFoundries made an announcement a couple of years ago. Samsung made an announcement just before DAC last year. But neither company has said anything much since. Of course the big noise… Read More


FDSOI jump-start 2015 in Tokyo this week

FDSOI jump-start 2015 in Tokyo this week
by Eric Esteve on 01-19-2015 at 4:38 am

This news in May 2014 that Samsung had licensed FD-SOI Technology from ST-Microelectronics was really amazing, as most of the industry was expecting this kind of agreement, but not with the #2 SC Company. But since May 2014 the news flow has been quite reduced, we can imagine that both SC companies had a lot work to do for transforming… Read More


IEDM: FD-SOI Down to 10nm

IEDM: FD-SOI Down to 10nm
by Paul McLellan on 01-03-2015 at 1:48 pm

Image RemovedThe big picture is that planar semiconductor transistors don’t really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner.… Read More