FD-SOI, an Opportunity for China?

FD-SOI, an Opportunity for China?
by Paul McLellan on 11-04-2014 at 11:00 pm

Image RemovedLast month in Shanghai was a meeting of the FD-SOI consortium. The focus of the meeting was largely on the suitability of using FD-SOI to serve the Chinese market. The fabs in China are not right on the bleeding edge and are very cost-sensitive so 28nm is probably as advanced as they will get for a long time if not indefinitely.… Read More


How ST Designs with Layout Dependent Effects (LDE)

How ST Designs with Layout Dependent Effects (LDE)
by Daniel Payne on 10-15-2014 at 12:00 am

I first visited STat their Agrate, Italy site where Flash memory development is done. At DACthis year Antonio Bogani talked about how ST designs with LDE while using EDA tools and a PDK (Process Design Kit) from Cadence. They recorded the 17 minute presentation, and you can view it herewithout having to register. Antonio’s… Read More


FD-SOI at 14nm

FD-SOI at 14nm
by Paul McLellan on 08-17-2014 at 7:01 am

At the recent Semicon West, Michel Haond of ST Microelectronics had a presentation on 14nm FD-SOI, or what they more lengthily call UTBB FD-SOI (which when you expand it all out comes to Ultra Thin Body and Buried-Oxide Fully Depleted Silicon on Insulator). When Chenming Hu (or whoever in his group) came up with the term FinFET it … Read More


Analog Model Equivalence Checking Accelerates SoC Verification

Analog Model Equivalence Checking Accelerates SoC Verification
by Pawan Fangaria on 08-09-2014 at 7:30 pm

In the race to reduce verification time for ever growing sizes of SoCs, various techniques are being adopted at different levels in the design chain, functional verification being of utmost priority. In an analog-digital mixed design, which is the case with most of the SoCs, the Spice simulation of analog components is the limiting… Read More


FD-SOI: 20nm Performance at 28nm Cost

FD-SOI: 20nm Performance at 28nm Cost
by Paul McLellan on 07-28-2014 at 8:01 am

There has been a lot of controversy about whether FD-SOI is or is not cheaper to manufacture than FinFET. Since right now FinFET is a 16nm process (22nm for Intel) and FD-SOI is, for now, a 28nm process it is not entirely clear how useful a comparison this is. Scotten Jones has very detailed process cost modeling software (that is what… Read More


FD-SOI Not Just For France Any More, China Signs On?

FD-SOI Not Just For France Any More, China Signs On?
by Paul McLellan on 04-30-2014 at 9:07 pm

Image RemovedThe COO of ST Microelectronics, Jean-Marc Chery announced that they have signed a new foundry agreement for FD-SOI. What he actually said doesn’t reveal who the foundry in question is:“We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands theRead More


FD-SOI Better Than FinFET?

FD-SOI Better Than FinFET?
by Paul McLellan on 04-27-2014 at 9:16 am

As I said earlier in the month, I was going to be talking about FD-SOI at the Electronic Design Process Symposium (EDPS) in Monterey. I am not especially an expert on FD-SOI but I know enough to be dangerous and given that we were already talking about FinFET and 3D/2.5D chips, it fitted in nicely.

The 10,000 foot view is that FD-SOI has… Read More


ISSCC: Analog-Digital Converter in FD-SOI

ISSCC: Analog-Digital Converter in FD-SOI
by Paul McLellan on 02-20-2014 at 11:50 am

Image RemovedThe International Solid-State Circuits Conference (ISSCC) was last week in San Francisco. Stéphane Le Tual, Pratap Narayan Singh, Christophe Curis, Pierre Dautriche, all from STMicroelectronics presented a paper on A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOIRead More


Dual Advantage of Intelligent Power Integrity Analysis

Dual Advantage of Intelligent Power Integrity Analysis
by Pawan Fangaria on 02-03-2014 at 9:30 am

Often it is considered safer to be pessimistic in estimating IR-drop to maintain power integrity of semiconductor designs; however that leads to the use of extra buffering and routing resources which may not be necessary. In modern high speed, high density SoCs having multiple blocks, memories, analog IPs with different functionalities… Read More


What will drive MEMS to drive I-o-T and I-o-P?

What will drive MEMS to drive I-o-T and I-o-P?
by Pawan Fangaria on 01-27-2014 at 5:45 am

Image Removed Image RemovedBy I-o-P, I mean Internet-of-People- I couldn’t think of anything better than this to describe a technology which becomes your custodian for everything you do; you may consider it as your good companion through life or an invariably controlling spy. This is obvious with the embedded sensor techno-products… Read More