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ISSCC: Analog-Digital Converter in FD-SOI

ISSCC: Analog-Digital Converter in FD-SOI
by Paul McLellan on 02-20-2014 at 11:50 am

 The International Solid-State Circuits Conference (ISSCC) was last week in San Francisco. Stéphane Le Tual, Pratap Narayan Singh, Christophe Curis, Pierre Dautriche, all from STMicroelectronics presented a paper on A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology.

Modern wireline communication devices whether over copper or fiber require a high-speed analog-digital converter (ADC ) in their receive path to do the digital equalization, or to recover the complex-modulated information. A 6b 10GS/s ADC able to acquire up to 20GHz input signal frequency and showing 5.3 ENOB in Nyquist condition was presented at ISSCC. It is based on a Master Track & Hold (T&H) followed by a time-interleaved synchronous SAR ADC, thus avoiding the need for any kind of skew or bandwidth calibration. Ultra Thin Body and BOX Fully Depleted SOI (UTBB FDSOI) 28nm CMOS technology is used for its fast switching and regenerating capability. The core ADC consumes 32mW from 1V power supply and occupies 0.009mm[SUP]2[/SUP] area. The Figure of Merit (FoM) is 81fJ/conversion step.

Let’s focus on the implementation which is in ST’s 28nm FD-SOI process. Just as a reminder, FD-SOI is an alternative to FinFET which has some big advantages in being architecturally very similar to a “normal” planar process. FinFET has quantized transistor sizes which makes analog design challenging. ST have picked this transistor architecture and a couple of other manufacturers are in the FD-SOI consortium, most notably GlobalFoundries and UMC (but not TSMC which is committed completely to FinFET). This is a very high performance ADC and thus an example of complex high-precision analog design in FD-SOI.

Previously at ISSCC and other conferences, earlier designs have been presented in processes ranging from 65nm CMOS to 32nm SOI. Looking at the table above, you can see that while having similar characteristics as sampling rate or resolution, with the plus of having the smallest implementation (even if not an apples to apples comparison due to technology scaling), the best power consumption, best characteristics and, big advantage vs the earlier results, no need of gain/skew calibration for reaching such state-of-the-art results when for all the others it is mandatory.

To summarize, the block uses the efficiency of the pure passive “sampling and redistribute” concept for signals up to 20GHz. Together with the low-power capability of the 28nm CMOS UTBB FDSOI technology, ST could reach 10GS/s operation while keeping the power consumption at 32mW under 1V supply with a block that is just 0.009mm[SUP]2[/SUP].

The ISSCC website is here. If you have access to the proceedings then it is paper 22.3.

More articles by Paul McLellan…

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