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$1 Billion IP & VIP sales by 2017?

$1 Billion IP & VIP sales by 2017?
by Eric Esteve on 02-20-2014 at 9:58 am

We are not talking about ARM Ltd., as the IP vendor has already passed the $1B sales in 2013. In fact, we are not talking about a single IP vendor; this $1B mark will be passed by two IP market segments: Interface and Verification IP. In fact these two segments are very close together. When an IP is developed to support a specific Interface protocol standard, a related Verification IP (VIP) is needed at the same time. This VIP is firstly used by be design team in charge of the related IP development, to verify the IP compliance in respect with the specific protocol. And, by the way, we understand why the VIP has to be designed by a different team, not necessarily from a different company, but the architects should be two different persons. This strategy is the only way to avoid the equivalent of the “common mode error” in aeronautics.

If you list every protocol standard, and each new release of this Interface standard, you can identify the related VIP in the vendor port-folio:

  • USB (USB 2.0, USB 3.0 and 3.1, HSIC, SSIC)
  • PCI express (PCIe gen-1, gen-2, gen-3 and yet to be released gen-4, M-PCIe)
  • MIPI (D-PHY, CSI-2, DSI, M-PHY, CSI-3, DSI-2, LLI, SlimBus, UniPro, etc.)

Then, adding Ethernet, SATA, SAS, HDMI, DisplayPort, I2C, JTAG, NVM Express, protocols, you have covered most of the potential VIP products. It’s interesting to notice that the Design IP and related VIP are acting as the hand and the glove: it’s complementary. Thus, if you have to verify a PCI Express Root Port IP, the VIP will act as an Endpoint agent, and conversely.

IPNEST is the well-known analyst expert of the Interface IP market (see: Interface IP Survey), it was a natural move to analyze the Verification IP market (this was IPNEST’s customer opinion). In fact, the market dynamics for Design IP and VIP are quite different. When starting a SoC design, the project manager easily identify the functions (IP) which may be outsourced, in order for the design team to focus on the company differentiators and speed up the SoC release for Time To Market (TTM) enhancement. Then the make versus buy analysis is run, the IP outsourced when it makes sense.

The Verification IP outsourcing follows different rules. The project manager may decide to buy VIP externally when his team is developing the related Design IP. In this case, the primary goal is to validate the IP itself, and the task is known to be CPU intensive, consuming as well many VIP Licenses (or token, or seats) and leading to a high VIP cost. The project manager may again decide to outsource or develop internally this VIP. Interesting for the VIP vendor, even if the Design IP is outsourced, and reputedly 100% functional, the project manager may have to outsource VIP, but the goal is different. In this case, he will need the VIP to run the complete chip verification, during the functional simulations. It’s to be noticed that when a Design IP functionality implies that most of the communication with the SoC will pass through it, the related VIP will become crucial, which translate in term of EDA expenses, as the team will need more VIP tokens (or seats) than for another function within the SoC (which could be more complex from a functional view point). This example help introducing the concept of “VIP Expenses” rather than “VIP License” cost. IPNEST has decided to segment each VIP segment in respect with the following parameters:

  • IP Internally designed, or outsourced
  • On the edge IP (first use), or re-used IP
  • Chip maker: Tier 1, or Tier 2

Thus the VIP expenses (not license or token) are evaluated for every protocol standard, and every segment (the A, B, C and D in the above table.
By using the “Interface IP survey”, we can extract the number of design starts by protocol standard, as we have evaluated the IP License Average Selling Price (ASP), covering the first segment: IP externally sourced. Then, we have to make an evaluation of the design starts including internally designed IP to cover the second segment. In the VIP survey, most of the intelligence is inserted in the various VIP expenses by protocol. To comfort this evaluation, we have run interviews with chip makers, representative of the Tier 1 and Tier 2 segments.

At this point, we realize that we have only covered 50% of the VIP market! In fact, a very important segment of this market, in term of business, is the sale of “Memory Models”. This was the initial Denali business, and this is an ever increasing segment. If you make the acquisition of the “Verification IP Survey”, you will see how IPNEST has dealt with this part of the VIP market. But this was not enough: the internal bus, like AMBA or OCP, also generates a VIP need, to speed up the SoC validation. These various VIP segments are also evaluated.

Maybe you don’t care about the methodology, and just want to know the bottom line result? This is a human behavior, and IPNEST had to deal with such request! If you consider that such an answer (VIP market size in 2013) is the result of a real work, running segmentation, design start evaluation, spending time to verify, as far as possible the various steps, you understand why only the happy few buying the VIP Survey will benefit from this information…

That I can tell you, free of charge, is that the cumulated Interface IP and VIP market segments will weigh more than $1 billion in 2017.

Eric Esteve from IPNEST

Table of Content for “Interface IP Survey 2008-2012 – Forecast 2013-2017” available here

Table of Content for “Verification IP Survey” available here

More Articles by Eric Esteve…..

lang: en_US

You probably better know why IPNEST is the leader on the Interface IP and VIP dedicated surveys, enjoying this long customer list:

Synopsys, (US)
Cadence, (US)
Rambus, (US)
Arasan, (US)
Denali, (US) now Cadence
Snowbush, (Canada) now Semtech
MoSys, (US)
Cast, (US)
eSilicon, (US)
True Circuits, (US)
NW Logic, (US)
Analog Bits, (US)
Open Silicon,(US)
Texas Instruments, (US)

PLDA
, (France)
Evatronix,(Poland)
HDL DH, (Serbia)
STMicroelectronics (France)

Inventure
, (Japan) now Synopsys
“Foundry” (Taiwan)
GUC, (Taiwan)
GDA, (India)
KSIA, (Korea)
Sony, (Japan)
SilabTech, (India)
Fabless, (Taiwan)


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