WP_Term Object
(
    [term_id] => 72
    [name] => STMicroelectronics
    [slug] => stmicroelectronics
    [term_group] => 0
    [term_taxonomy_id] => 72
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 77
    [filter] => raw
    [cat_ID] => 72
    [category_count] => 77
    [category_description] => 
    [cat_name] => STMicroelectronics
    [category_nicename] => stmicroelectronics
    [category_parent] => 14433
    [is_post] => 1
)

IEDM: FD-SOI Down to 10nm

IEDM: FD-SOI Down to 10nm
by Paul McLellan on 01-03-2015 at 1:48 pm

 The big picture is that planar semiconductor transistors don’t really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner. One way to do this is to make it into a thin fin and wrap the gate around it. That is what Intel, IBM and TSMC have all done and I reported on their papers at IEDM last month.

See IEDM: TSMC, Intel and IBM 14/16nm Processes

The other alternative is to build the channel as a thin layer on an insulating wafer (SOI). This is the approach that has been pioneered by ST Microelectronics and its partners. They also presented at IEDM in a paper entitled FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10um Node. The paper has a long list of authors from ST, CEA-LETI, IBM, Soitec, and Albany Nano Tech.

Planar fully depleted silicon-on-insulator (FDSOI) technology represents an important device architecture for continued CMOS scaling. Its advantages include excellent short-channel electrostatics, un-doped channels and effective back bias for performance boost and leakage lowering. Moreover, FDSOI is fabricated using a more conventional, lower-cost process than more complex FinFET architectures. Researchers from STMicroelectronics and the IBM Technology Development Alliance discussed the successful implementation of strained FDSOI devices with gate lengths, spacers & buried oxide (BOX) dimensions compatible with design rules of the 10nm technology node.

Two additional enabling elements for scaling FDSOI devices to the 10nm node were reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also will report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 μA/μm for NFET at Ioff=1 nA/um, and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 μA/μm at Ioff=1 nA/um.

More articles by Paul McLellan…


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