Greater demand for more data exchange within data centers is being driven by mobile computing and the Internet-of-Everything. In 2011, it was estimated that over 1 Zettabytes (ZB) of data was pushed through the internet. That’s 1×10[SUP]21[/SUP] bytes of data. And, that amount has been doubling every 3 years since. Given that rate, it is estimated that by 2017 we will be looking at 7ZB of data being exchanged over the internet per year. This semiconductor industry has responded with 100Gbps transceivers and work is active on 400Gbps versions. With 400Gbps comes two additional pushes. The first is a move to longer reach fiber-based connections to overcome copper’s current limitation of 100 meters. The fiber/optical connections promise up to 2km reach at these speeds and higher. The second is the push towards using fiber/optical for ultra-short reach board-to-board and even chip-to-chip connections where 10’s of Terabytes per second rates are desired (see figure).
We have heard a lot about integrated photonics and how it will be deployed to address bandwidth challenges, yet we have not seen adoption of photonic processes by the major fabs. Then I read chapter 10, in a recently published book entitled, Silicon Photonics III and I was stunned. The chapter was contributed by a team from ST Microelectronicswhere they published no less than 35 pages detailing their efforts to integrate a photonics process into one of their 300mm SOI fabs. How did I miss this? Until reading this, everything else I had read about photonic detailed achievements in laboratories and universities where photonic engineers were investigating new materials or defining better ways to modulate or control light. Chapter 10 put things into a totally different light (pun intended). This was a group of serious semiconductor professionals doing what they do best. They were integrating a process in preparation for large scale production.
You can tell things are getting serious when you starting reading phrases such as these:
– Qualification runs
– Reliability test chips
– Optical & Electrical wafer sorting
– Production test methodologies and equipment
– Photonic process integration and process control
– Process monitoring / characterization
– Silicon-based model extraction
– Optical SPICE modeling
– Silicon-to-SPICE model correlation (see figure)
– Stress and temperature dependent modeling
Add to this, seeing wafer maps showing cross-wafer parameter variance and whisker charts showing lot-to-lot performance of various metrics and you know that you are no longer looking at an experiment in a lab. The ST team was detailing what they were doing to bring about a production worthy optical platform. Then consider all of this work is wrapped around the words “300mm” and you also realize that a major investment is being made even as we speak. One shudders to think of how many more resources are being deployed working on products to fill this line once it is fully up and running. The good news for ST is that they claim that this effort uses the same fab equipment as their regular SOI lines, at least on the fabrication side. That means new capital investments were minimal. That is not to say however that this photonic process is the same as their existing SOI logic processes. In fact, the book chapter is littered with new three and four letter acronyms that would imply otherwise. Things like DSOI which stands for double-SOI where ST is modifying the base wafer to improve the surface coupling efficiency of gratings used to bring light on and off of the IC. They did this by adding a polysilicon layer buried in the BOX to create the equivalent of a Bragg reflector that reduces the amount of light lost through the silicon. Additionally, they added the ability to do multiple partial etch steps enabling them to etch to different depths in different areas of the die. This enables ST to optimize the photonic wave guides for lower loss and tighter turns, which means smaller footprint die. There has also been a considerable amount of work done to quantify the effects of stress and temperature on the various photonic components. This is because ST knows that they will be flip-chip assembling electronic die on top of photonic die and interposers and the photonics must work even when stressed by Cu Pillars and TSVs (through-silicon-vias) and by the heat generated from the electrical die.
While there is still much work to be done, this article to me was a watershed event as it represents a real shift of photonics out of the labs and into the fabs. It doesn’t yet represent a fabless photonic eco-system but moving silicon photonics into a 300mm fab is a serious step forward for photonics and that’s good for anyone working in this space.Share this post via: