Mentor’s New Emulator

Mentor’s New Emulator
by Paul McLellan on 04-25-2012 at 8:00 am

Mentor announced the latest version of their Veloce emulator at the Globalpress briefing in Santa Cruz. The announcement is in two parts. The first is that they have designed a new custom chip with twice the performance and twice the capacity. It supports up to two billion gate designs and many software engineers. Surprisingly … Read More


Kathryn Kranen Interview in San Jose Mercury News

Kathryn Kranen Interview in San Jose Mercury News
by Paul McLellan on 03-07-2012 at 1:22 pm

There is an interview in the San Jose Mercury News with Kathryn Kranen, Jasper’s CEO. Of course the Mercury is a general newspaper and can’t expect most of its readership to have a clue what EDA is, never mind formal verification. It’s a similar problem to the one we all have when we try and explain to our families… Read More


Verdi’s 3rd Symphony

Verdi’s 3rd Symphony
by Paul McLellan on 03-05-2012 at 7:00 am

The first version of the debug platform Verdi (then called Debussy) dates back to 1996 over 15 years ago. The second version was released in 2002. And now SpringSoft is releasing the 3rd version Verdi[SUP]3[/SUP]which is a completely new generation. A tool environment like Verdi seems to need to be completely refreshed about every… Read More


Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge… Read More


Formally verifying protocols

Formally verifying protocols
by Paul McLellan on 11-15-2011 at 1:19 pm

I attended much of the Jasper users’ group a week ago. There were several interesting presentations that I can’t just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper’s products on a daily basis.

But for me the most interesting presentations were several… Read More


Noise Coupling

Noise Coupling
by Paul McLellan on 10-24-2011 at 8:47 am

One of the challenges of designing a modern SoC is that the digital parts of the circuit are really something that in an ideal world you’d keep as far away from the analog as possible. The digital parts of the circuit generate large amounts of noise, especially in the power supply and in the substrate, two areas where it is impossible… Read More


Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards

Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards
by Eric Esteve on 09-27-2011 at 1:56 am

The mobile devices market is simply exploding, with smartphones shipmentgoing up to the sky, tabletsemerging so fast that some people think it will replace PC (but this is still to be confirmed…). This lead mobile SoC designs to integrate increasingly more features, to support customer needs for more computing power and sophisticated… Read More


When analog/RF/mixed-signal IC design meets nanometer CMOS geometries!

When analog/RF/mixed-signal IC design meets nanometer CMOS geometries!
by Daniel Nenni on 09-13-2011 at 9:22 am

In working with TSMC and GlobalFoundries on AMS design reference flows I have experienced first hand the increasing verification challenges of nanometer analog, RF, and mixed-signal circuits. Tools in this area have to be both silicon accurate and blindingly fast! Berkeley Design Automation is one of the key vendors in this … Read More


What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?

What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?
by Eric Esteve on 09-05-2011 at 4:53 am

Even if nSys acquisition by Synopsys will not have a major impact on Synopsys’ balance sheet, it is a kind of earthquake in the Verification market landscape. After the Denali acquisition by Cadence in 2010, nSys was most probably the market leader in verification IP, if we look at the independent VIP providers (excluding Cadence).… Read More


Speeding Verification of FPGA Prototype Boards

Speeding Verification of FPGA Prototype Boards
by Paul McLellan on 08-09-2011 at 5:42 pm

It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total. Simulation is increasingly too slow, especially when software … Read More