Automating Analog Verification in Virtuoso

Automating Analog Verification in Virtuoso
by Daniel Payne on 03-31-2014 at 2:00 pm

Digital designers have been automating the functional verification process for many years now, however when you talk to an analog designer about how they do verification you quickly realize that the typical process is quite ad-hoc and little automated. Necessity does create an opportunity so the software engineers at MethodicsRead More


Top 10 Reasons to Use Vivado Design Suite

Top 10 Reasons to Use Vivado Design Suite
by Paul McLellan on 03-23-2014 at 7:05 am

Here are the top 10 reasons to use the Xilinx Vivado Design Suite to design your All Programmable Devices:

Reason number 10: Accelerate verification by over 100XThe Vivado Design Suite System Edition lets you do design at the C, C++ or systemC level. But a side-benefit is that you can use these languages for verification at performances… Read More


Jasper at DVCon and EJUG

Jasper at DVCon and EJUG
by Paul McLellan on 03-13-2014 at 7:05 pm

The Jasper European User Group meeting (EJUG) is coming up in a couple of weeks. It will be held in the Munich Hilton (which I have stayed in many times, the S-bahn from the airport pretty much stops in the basement) on April 2nd.

The schedule for the day is:
9:00 AM – Registration and continental breakfast
9:30 AM – Jasper… Read More


Now even I can spot bad UVM

Now even I can spot bad UVM
by Don Dingee on 03-11-2014 at 8:30 pm

Most programmers can read a code snippet and spot errors, given enough hours in the day, sufficient caffeine, and the right lens prescription. As lines of code run rampant, with more unfamiliar third-party code in the mix, interprocedural and data flow issues become more important – and harder to spot.

Verification IP particularly… Read More


Semiconductor Strategy – From Productivity to Profitability

Semiconductor Strategy – From Productivity to Profitability
by Pawan Fangaria on 03-08-2014 at 8:30 am

The semiconductor industry seems to be the most challenged in terms of cost of error; a delay of 3 months in product development cycle can reduce revenue by about 27% and that of 6 months can reduce it by almost half; competition is rife, pushing the products to next generation (with more functionality, low power, high performance,… Read More


Synopsys Announces Verification Compiler

Synopsys Announces Verification Compiler
by Paul McLellan on 03-04-2014 at 8:00 am

Integration is often an underrated attribute of good tools, compared to raw performance and technology. But these days integration is differentiation (try telling that to your calculus teacher). Today at DVCon Synopsys announced Verification Compiler which integrates pretty much all of Synopsys’s verification technologies… Read More


Synopsys’s Next Generation Emulator, ZeBu Server-3

Synopsys’s Next Generation Emulator, ZeBu Server-3
by Paul McLellan on 02-28-2014 at 12:17 pm

Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier… Read More


Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe

Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe
by Paul McLellan on 02-28-2014 at 8:31 am

Yesterday evening was EDAC’s first mixer. I assume the first of a regular event. It was held in Mountain View in the old train station which is now the Savvy Cellar wine bar. I had a nice glass of rosé from Provence that reminded me of the years that I lived in the south of France. Some of the money we spent went to charity, to the Mountain… Read More


A Methodology for Assertion Reuse in SoC Designs

A Methodology for Assertion Reuse in SoC Designs
by Daniel Payne on 02-21-2014 at 4:24 pm

As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to … Read More


Verifying DRC Decks and Design Rule Specifications

Verifying DRC Decks and Design Rule Specifications
by Daniel Nenni on 02-19-2014 at 8:00 am

DRVerify is part of the iDRM design rule compiler platform from Sage DA, something that I have been personally involved with for the past three years. DRVerify is mainly used to verify third party design rule check (DRC) decks and ensure that they correctly, completely and accurately represent the design rule specification. In… Read More