Imec technology forum 2018 – the future of scaling

At the Imec technology forum in Belgium, Dan Mocuta and Juliana Radu presented “Evolution and Disruption: A Perspective on Logic Scaling and Beyond”, I also had a chance to sit down with Dan and discuss the presentation.

Device scaling
Scaling of devices will only get you so far, you need to look at new devices and new materials. For new materials SiGe for channels is the most likely next material. Authors note, there was a lot of discussion of SiGe PMOS channels for 5nm at IEDM in December of last year.

You can use circuit level design to augment device level scaling that is slowing down but they are one-time kind of scaling boosters and you have to come up with something new for each new generation. Figure 1 illustrates some device level scaling boosters that are being considered or implemented.

Authors note, some of the scaling boosters in figure 1 are in use now, for example super vias in TSMC 10nm, dual STI in multiple FinFET technologies, single diffusion break in multiple technologies and self-aligned gate in Intel’s 10nm process.

From a device scaling perspective, the goal is to stay on FinFETs as long as possible for cost and control reasons but contacted poly pitch (CPP) scaling is slowing and moving to horizontal nanowires/nanosheets (HNW/HNS) provides additional CPP scaling. Imec has demonstrated HNW/HNS but it is not their scope to carry it further. Companies interested in commercializing the technology must carry the work forward.

System optimization
To continue scaling you must look at the system and optimize the system and technology. There are three approaches:

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• Co integration – co integrate devices, for examples IBM 14nm has FinFETs over embedded trench DRAM fabricated in the substrate. Or there is the proposed CFET devices where nFET and pFET devices are stacked on top of each other.
• Sequential 3D – fabricate a device up to Middle Of Line (MOL) and then bond a wafer on top, thin the bonded wafer and fabricate another layer of devices in the bonded wafer, for example SRAM over logic.
• 3D IC – fabricate complete devices and then stack them using Through Silicon Vias (TSV) and or Interposers.Figure 2 summarizes the three approaches.
  
  Figure 2. System Technology Co Optimization (STCO) Driven (Disruptive) Future Scaling.

  Figure 3 provide more information on the CFET concept. Stacking an nFET over a pFET into 2 decks can result in a 40% structural gain in SRAM scaling. Authors note, there are groups working on extending this concept to multiple decks, I have even seen a 7 deck proposal that relaxes lithography rules to 14nm but achieve 1xnm node scaling.

  
  Figure 3. Disruptive Next Generation Device: CFET.

  Figure 4 illustrates how a multi core microprocessor can be scaled using 3D integration. The advantage of this technique is that each block of the microprocessor can be implemented in the optimum technology. Breaking up the cores, memory and internal/external interconnect allows a memory optimized process to be used for memory, a core performance optimized technology to be used for the cores and a relaxed technology for the I/O. This type of partitioning and optimization can address performance and cost but there are cooling challenges with this approach.

  
  Figure 4. 3D-SOC: Functional Partitioning for High Performance.

  
  Conclusion
  As traditional device scaling slows down there are multiple options for new devices and 3D integration schemes to continue scaling.