For Halloween this week we thought it would be appropriate to talk about things that strike fear into the hearts of semiconductor makers and process engineers toiling away in fabs. Do I want to do multi-patterning with the huge increase in complexity, number of steps, masks and tools or do I want to do EUV with unproven tools, unproven process & materials and little process control?
It’s like choosing between death by firing squad and death by hanging….neither one is particularly palatable. The choice seems to come down to the lesser of two evils but it is as critically important to chipmakers as it is to tool makers as it defines who wins and loses on both sides. It is also critical to the continuation of Moore’s law on which depends the entire tech industry…..so choose wisely.
We see the beginnings of a shift back to litho centric transistor formation and away from multi patterning. Not just because EUV now works or is cheaper but because it is the lesser of two problematic choices facing the industry.
The industry was surprised by the rapidity of the shift to multipatterning as it seemed to originally be more of a stopgap process to keep Moore’s law on track. Today we could potentially see a more rapid move to EUV prior to its true readiness for HVM as multipatterning could be facing issues.
Much as we were early on the multipatterning bandwagon a number of years ago, we are likely a bit early on EUV, after being a critic for many years of delays. We are also not jumping on the EUV bandwagon out of blind faith but rather despite understanding all the issues facing the industry.
Two key decision drivers
We think there are two key decision drivers that will push the industry away from multi patterning towards EUV even before EUV is fully HVM ready and before EUV could claim a cost savings .
The first issue is that multipatterning may be running out of gas sooner than expected. We had half heartedly joked well over a year ago about the industry going to “oct patterning” (eight patterns) as a continuation of Moore’s law. It felt like the industry would just see a linear progression in complexity relative to the number of patterns that could be continued ad nauseaum . Well, its turned out that the complexity increase is more exponential as non deterministic problems have been cropping up in quad patterning at many manufacturers we have spoken to. These sort of “spooky” problems are not very good when you are trying to run the ultimate exercise in deterministic process flow in a fab.
The second issue is that transistors formed with EUV are just plain better. Transistor dimensions and design are hyper critical and do not tolerate “fuzziness” very well. Whereas it doesn’t matter very much if the wires interconnecting the transistors aren’t perfectly straight smooth lines of constant thickness, these attributes in a transistor can kill the performance. better transistors mean faster speed and lower power and the biggest semiconductor user in the world, Apple, wants the best.
There are certainly other factors to consider, like cost, but right now, we think the decision is being forced by these two key issues that could push the industry to EUV faster, before its really ready for prime time.
The driver behind the drivers…Apple
We think Apple is keenly aware and keenly focused on the transistor performance issue. They want lower power for better battery performance and faster speeds to handle AI, VR, AR and all other high end applications coming to a phone near you.
Samsung and TSMC are in an all out race to curry Apple’s favor. Even though TSMC has the upper hand versus “frenemy” Samsung, Samsung wants to get EUV first to try to lure Apple back to their foundry. TSMC has been a long time “doubter” of EUV but has now reversed course and has to keep up with Samsung and push EUV to keep Apple happy.
We have heard rumors that Apple may have subsidized TSMC’s EUV costs in some way and in return gotten some sort of “first dibs” on EUV capacity (not that they don’t have first dibs anyway). Samsung still would like to have an advantage over Apple with its own phones and obviously wouldn’t mind enhanced transistor performance.
Where does this leave Intel?
The funny thing is that Intel is not racing anyone or in the running for Apple’s business so they don’t have as much motivation to commit “unnatural acts” to get EUV running just to keep a customer happy or have expensive bragging rights. Just who are they competing against anyway? Certainly not AMD. Intel has not been in a panic to get 10NM out the door even though its very late. They are taking their sweet time. Intel has clearly said that it has a 7NM solution with existing techniques and doesn’t need no stinkin EUV.
Intel in fact has voted with their feet. Their capital spending says it all. While Samsung and TSMC have been spending like drunken sailors, Intel has been much slower and this recently announced quarter even dropped capex plans a bit. Intel is marching to the beat of their own drummer.
This all suggests that Intel will likely be last of the big three to implement EUV and probably only at 5NM. We find it funny and a bit poetic that Intel is a remaining major shareholder in ASML and is benefiting from the rumors of Samsung placing a large order with ASML driving up the value of Intel’s holdings in ASML stock.
ASML & EUV issues
Much is still up in the air about EUV. While reliability and uptime have gotten better, they are not great. Many issues remain a veritable laundry list; throughput, pellicles, resist, shot noise, tool to tool matching, line edge roughness, mask inspection, defect free mask, droplet generator, mask blanks and on and on… ASML has been less than completely forthcoming about issues and progress.
As an example, pellicles remain a large, unclear (pun intended…) issue. They are a key issue as they impact both defects and throughput. Pellicles also prevent EBeam inspection of a mask and have to be removed before EBeam inspection can be done, which itself is problematic. ASML talks about a 10% loss of 250W of EUV power but the reality is much worse and more negatively impactful on throughput. The reality is that the 250 watts of EUV passes through 3 pellicles on the way to the wafer. The EUV passes through the pellicle on the travel to the mask and on the travel away from the mask. The EUV also passes through another pellicle called a DGL (dynamic gas lock- essentially a pellicle to prevent resist generated crap from getting on the lenses rather than machine generated crap getting on the mask, which the other pellicle takes care of). Also, right now, pellicle loss is about 15% not the future “planned” 10% that ASML quotes. so 250 Watts of EUV is really 153.5 Watts or roughly a 40% loss (250W X .85 X.85 X.85) of throughput (ouch!).
We have also tried to model the costs of EUV and the cost savings that ASML talks about but we have a hard time getting there from here. Very simply, if one EUV step can replace 3-4 times as many multipatterning steps it would seem to be a cost saver? This is not really the case right now as the cost of EUV masks are at least 3-4 times higher in theoretical cost (and in reality higher than that as yields are so low). If we look at tool costs and uptime and current throughput it only gets worse. So to be very clear, no one is doing EUV for the cost savings.
Despite all this we think that EUV may accelerate anyway for the two key reasons we outline above.
KLAC and EUV Mask Inspection“Patriot Games”
EUV mask inspection is best done with the same wavelength of light used in the EUV scanner so you can see what the EUV scanner will see. You can also obviously “see through” the pellicle.
KLAC killed its “Actinic” (at wavelength) product a number of years ago when it couldn’t get the industry to cough up $500M development costs. KLAC also likely thought at the time that EUV might never happen. Just last week, KLA reversed course and announced a multi EBeam tool to inspect EUV masks. Perhaps they figured out that EUV was really going to happen or perhaps it was EBeam products from ASML, AMAT and NuFlare that brought them back or more likely both.
The problem is that EBeam EUV mask inspection is very slow and still not a final answer. Actinic is the “golden rule” for EUV and it seems that Lasertec of Japan is working on a tool and may have it out in the not too distant future. We have heard of inspect times of 24 hours on the tool. More interestingly we have heard rumor that Intel is helping out Lasertec and sponsoring the tool in some way. This is made more interesting in that Intel wouldn’t give up money to KLA for an actinic tool. Perhaps its real or perhaps just a stalking horse to get KLA back into the actinic game…either way EUV wins.
We would not be surprised to see KLA’s actinic inspection tool rise back from the dead much like Jason in the Friday the 13th movie series.
Actinic inspection of EUV masks run in to the same issue that EUV scanners have…namely source power, as generating enough EUV light is hard to do to either print or inspect using EUV wavelengths. This problem will be the same for everyone and remains a hurdle for any EUV actinic inspection tool.
In the meantime, optical inspection isn’t all as good as KLA suggests and really isn’t quite good enough to be a real “stopgap” until the release of their multi beam tool. The “Teron” optical inspection tool is not a “complete solution” . After doing multiple passes with different types of light and doing the math to compare and contrast the results to remove the noise from the signal it can still only find generalized areas of interest on the mask to look at more closely. After identifying those areas with the KLA tool, chip makers have to take the map from the KLA Teron and go on a more in depth study with a Zeiss “AIMS” tool to figure out if its a real defect or not. Teron cannot do the job alone and is thus a half ***** solution.
Finding mines in a minefield
An analogy we can use is that of finding mines in a minefield. In previous optical generations, a KLA mask inspection system could find all the mines a a mile square minefield with pinpoint accuracy and identify their type and lethality. Now, the Teron can only find a generalized square yard area in an EUV minefield where the dirt looks suspicious and someone has to go in with a bayonet and probe around to figure out wether its a mine or a tin can. Multi EBeam is just a thousand guys probing the minefield with bayonets.
Multipattern share loss impact on Dep & Etch (AMAT & LRCX)
Obviously both Applied and Lam have benefitted from multipatterning by selling a lot more dep and etch tools needed for multi patterning. On the other side of the coin, ASML has lost overall share in capital spending by chipmakers as the industry move to multipattern solutions rather than the non existant EUV.
The positive impact on both AMAT and LRCX (and TEL and others…) has been quite clear and a bit of an upside surprise over the last few years.
Multipatterning is far from going away and EUV will likely start out with double patterning. However we will not likely see the industry progress beyond quad patterning and may pull back a bit from it. Much as multipatterning ramped faster than the industry expected we think EUV could ramp faster than expected even though it remains less than ready for HVM.
To be very clear, the loss of multipatterning upside does not impact the 64, 128 or whatever number of layers needed for 3D NAND and all the upside of many layered 3D NAND remains solid. Lots of dep and etch tools are needed for 3D NAND. The capex share shift back towards litho will be more impactful on logic/foundry parts that are still primarily planar in nature.
Meaning…still a lot of dep and etch upside from memory but less from logic & foundry in the future.
To be even clearer, this is not an issue any time in the near term, next year or two. But really only starts as EUV starts at 7NM and becomes more apparent at 5NM when EUV takes more layers and looks a lot more like HVM.
While there is little to no near term impact, we write this note to get investors in the loop as to what to look for over the next couple of years in terms of shifting technology.
Obviously ASML has the most to gain as EUV starts up and hits its stride. KLAC has potential upside if it can get new products out on time and beat emerging competitors. KLA should have the upper hand here as its hard to overcome many decades of dominance in mask inspection and the years of know how and software.
AMAT and LRCX will see zero near term impact and the loss of some multipatterning in logic/foundry down the road which will likely be more than offset by memory but we continue to get nervous as memory spending is historically fickle.
Have a happy & safe Halloween…..and don’t get scared of the semi industry and technology that goes bump in the night……Share this post via: