From May 3[SUP]rd[/SUP] to May 6[SUP]th[/SUP] the 26[SUP]th[/SUP] annual Advanced Semiconductor Manufacturing Conference (ASMC) will be held in Saratoga Springs, New York.
The ASMC offers a unique view of challenges to the semiconductor industry focusing on things like defect reduction, metrology and fab operations. In my work on modeling of semiconductor costs I find the fab wide operational view of this conference particularly interesting.
I have been going through the advanced program identifying the papers that look to me to be the most interesting:
Monday – May 4[SUP]th[/SUP]
The conference opens with Keynotes on Monday morning. I am particularly interested in seeing Robert Maire present on “The Semiconductor Industry at an Economic Crossroads” There are so many new developments in the industry with Moore’s law slowing and the possible emergence of the Internet of Things that I am interested to hear his perspective.
In session 2 on Factory Optimization I am interested to see the papers on shortening cycle time and simulation use for 300mm fab automation. I have done a lot of work in the area of cycle time and cycle time is an area where I have questions come up a lot about benchmark cycle times and economic impact.
In the afternoon there is a paper in session 3 on Yield Enhancement/Methodology on collapse-free patterning for 20nm NAND flash that looks interesting.
In the evening there is an extensive poster session.
Tuesday May 5[SUP]th[/SUP]
In the morning, session 7 on Factory Optimization features several fab wide optimizations papers that look interesting covering performance indicators, equipment maintenance and green fabrication for energy savings. These type of papers often provide valuable insight into current fab state-of-the-art performance.
In the afternoon session 8 on Advanced Equipment and Materials has an interesting paper on wet etch of TiN and TaN for High-k metal gate fabrication.
Session 10 on Advanced Pattering has a paper on optimizing lithography tools for MEMS manufacturing. MEMS is an area where I do a lot of cost modeling.
Session 11 on Contamination Free Manufacturing has an interesting paper on backside and edge clean of III-V on silicon wafers. III-V on silicon is an area of intense research for sub 10nm logic processes.
Wednesday May 6[SUP]th[/SUP]
In the morning session 12 on Advanced Process Control features a paper on predictive maintenance. Variability is a huge detractor from fab performance and any time you can reduce variability for example by doing preventive maintenance in place of having random breakdowns you gain in efficiency.
Session 14 on 3D/TSV has a paper on enhanced etch process for TSV and deep silicon etch. TSV is an emerging area of great interest and etch is a major gating item in the process.
Session 15 on Advanced Equipment and Materials has a paper on multiple epitaxial films deposition for power semiconductors. Devices such as CoolMOS reduce on-resistance in high voltage power MOSFETs but require multiple Epitaxial layers. This should be an interesting view of how this is done at Infineon, a leader in this technology.
Of course conferences like this are also a great opportunity to network with key customers and partners.Share this post via: