Is a US Semiconductor Manufacturing Revival on the Way?

Is a US Semiconductor Manufacturing Revival on the Way?
by Anish Tolia on 08-13-2020 at 9:00 am

Is a US Semiconductor Manufacturing Revival on the Way

Two bits of recent news has excited people in the semiconductor manufacturing space. First TSMC (bit.ly/384joVr) announced their intention to invest $12 B dollars in a Fab in Arizona. Then came the Corona-driven bipartisan proposed $23B federal government investment in semiconductor manufacturing (nyti.ms/2YZzFqnl). … Read More


A Vibrant Semiconductor Manufacturing Model for the US

A Vibrant Semiconductor Manufacturing Model for the US
by Scott Jewler on 06-30-2020 at 10:00 am

Semiconductor Revenue 2019

Having spent the last 30 years in semiconductor manufacturing, eight years of this living and working in Asia, it is both exciting and unsettling to see renewed political interest in the revitalization of this industry in the United States. Gone are the days of ‘It doesn’t make any difference whether a country makes computer chipsRead More


efabless: Think GitHub for ICs and IP

efabless: Think GitHub for ICs and IP
by Daniel Nenni on 08-02-2016 at 4:00 pm

For those of you who don’t know, GitHub is the crowdsourcing version of the defacto industry standard GIT source code management software. Currently, more than 14 million people have deposited more than 35 million software projects (mostly open-source) on GitHub making it the largest host of source code in the world.

Now think… Read More


TSMC Leads Again with 3-D Packaging!

TSMC Leads Again with 3-D Packaging!
by Daniel Nenni on 05-24-2016 at 4:00 pm

Continuing to find new ways to extend Moore’s Law, the foundry and technology leader is ready to show off its wafer level system integration prowess with two scalable platforms targeting key growth markets.

CoWoS® (Chip-On-Wafer-On-Substrate) goes after high-performance applications, providing the highest bandwidth and… Read More


Process Development, CAD and Circuit Design

Process Development, CAD and Circuit Design
by Daniel Payne on 04-29-2016 at 7:00 am

Working at Intel as a circuit designer I clearly remember how there were three distinct groups: Process Development, CAD and Circuit Design. Each of the groups sat in a different part of the building in Aloha Oregon, we had different job titles, different degrees, spoke with different acronyms and yet we all had to work together … Read More


FinFET For Next-Gen Mobile and High-Performance Computing!

FinFET For Next-Gen Mobile and High-Performance Computing!
by Daniel Nenni on 02-22-2016 at 7:00 am

Evolving opportunities call for new and improved solutions to handle data, bandwidth and power. Moving forward, what will be the high-growth applications that drive product and technology innovation? The CAGRs for smartphone and data center continue to be very strong and healthy. … Read More


Pathfinding to an Optimal Chip/Package/Board Implementation

Pathfinding to an Optimal Chip/Package/Board Implementation
by Tom Dillinger on 02-04-2016 at 4:00 pm

A new term has entered the vernacular of electronic design engineering — pathfinding. The complexity of the functionality to be integrated and the myriad of chip, package, and board technologies available make the implementation decision a daunting task. Pathfinding refers to the method by which the design space of technology… Read More


The Death of Moore’s Law

The Death of Moore’s Law
by Michael Barger on 01-22-2016 at 12:00 pm

For the last several years, people have predicted the end of Moore’s Law. The reasoning is that there is a limit at which one can’t shrink transistors any further. A reoccurring comment has been “You can’t divide an atom.” I had assumed that its demise would be at the hands of a new paradigm like quantum computing. Now, with Intel’s … Read More


IEDM 2015 Blogs – Part 1 – Overview

IEDM 2015 Blogs – Part 1 – Overview
by Scotten Jones on 12-11-2015 at 7:00 am

The International Electron Devices Meeting (IEDM) is one of, if not the premier conference for semiconductor process technology. The 2015 meeting just finished up on Wednesday, December 9th.

This year’s meeting was held from Saturday, December 5[SUP]th[/SUP] through Wednesday, December 9[SUP]th[/SUP] in Washington DC.… Read More


Moore’s law limitations and gravitational collapse at lower process nodes

Moore’s law limitations and gravitational collapse at lower process nodes
by Vaibbhav Taraate on 10-05-2015 at 4:00 pm

As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for… Read More