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TSMC Leads Again with 3-D Packaging!

TSMC Leads Again with 3-D Packaging!
by Daniel Nenni on 05-24-2016 at 4:00 pm

Continuing to find new ways to extend Moore’s Law, the foundry and technology leader is ready to show off its wafer level system integration prowess with two scalable platforms targeting key growth markets.

CoWoS® (Chip-On-Wafer-On-Substrate) goes after high-performance applications, providing the highest bandwidth and pin count in a large package size. CoWoS is well-suited for diverse markets including graphics, networking and high-performance computing.

InFO, on the other hand, offers an ideal fit for today’s high-volume mobile, consumer and IoT devices that require compactness, integration flexibility and cost-effectiveness. Compared to existing options, InFO delivers a 20% thinner package, 20% performance gain and a 10% improvement in power dissipation. Based on wafer molding and metal process without a substrate, InFO’s reduced thickness and optimized performance make it a superior replacement for traditional Flip Chips.

With molding and metal between the logic die and the package I/Os there is neither an interposer nor a separate package – the metal and molding compound is the package. With its 5-micron metal pitch and no substrate, InFO makes for a very slim package (less than 1mm), reducing the thickness of smartphones and wearables for example. TSMC has also introduced InFO-POP with a DRAM die connected by a new “Through-InFO-Via,” and InFO_S that integrates multiple dies and will be launched by the end of 2016.

The following picture shows a cross-sectional view of an InFO PoP technology platform, with the logic chip at the bottom and a standard, industry-available DRAM package. The technologies are integrated using TIV to produce the thinnest solution in the industry. InFO PoP enables a thinner PoP stack with better routing density, higher operating frequency (Fmax), higher memory bandwidth DRAM and better heat dissipation.

In the critical area of InFO design support, TSMC helped pioneer EDA solutions for congruent IC and package design, including packaging layout and DRC signoff, along with its Open Innovation Platform® (OIP) partners last year. This ensures that InFO designs are fully compliant with TSMC’s packaging design rules and advances the company’s plans to provide a complete InFO design flow for its customers. Through OIP, the company is expanding InFO tool support, including electrical analysis and signoff such as RLC extraction for designers to analyze the parasitic impacts from InFO and its neighboring layers. The analysis of electrical migration and IP drop are also essential to ensure design reliability for the multiple dies on InFO. In addition, TSMC and its ecosystem partners are enhancing physical implementation with inter-die connection and physical signoff with inter-die DRC and LVS solutions.

To serve its customers as high-performance computing and mobile markets accelerate their pace of innovation, TSMC plans to invest not only on the front end silicon side, but the backend technology as well. The company has completed a new facility in Longtan InFO manufacturing and will begin volume production in 2Q16.

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