Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Secure-IC at the 2025 Design Automation Conference #62DACSecure-IC at DAC 2025: Building Trust into Tomorrow’s…Read More
The Sondrel transformation to Aion SIlicon!Ollie is a commercially astute senior leader with…Read More
For SoC designers attending DAC in June you probably want to check out the EDA vendors that enable design collaboration among your engineers and designers that are spread out across a building, campus or the globe. Dassault Systemes does offer tools and methodologies for: Design collaboration, requirements and IP management.… Read More
A couple of days ago Intel announced a collaboration with eASIC. Here is the opening paragraph of the press release:Intel Corporation today announced plans to develop integrated products with eASIC Corporation that combine processing performance and customizable hardware to meet the increasing demand for custom compute … Read More
It is hard to believe that Samsung is celebrating their 10[SUP]th[/SUP] anniversary in the foundry business this year. It certainly has not been an easy road but as of late you cannot argue with the results. Samsung is the first foundry to put 14nm silicon into smart phones, beating the #1 semiconductor company (Intel) and the #1 … Read More
We have been hearing about Intel’s Quark processor, which is based on its good old Pentium, making waves in IoT world. The CPU core of Quark is said to be the smallest in Intel. It is supposed to be inexpensive and extremely low in power; a perfect combination for IoT devices. The Pentium architecture equips the processor to perform… Read More
That was said by the novelist Samuel Butler, but it is not a bad description of why you should spend the Sunday at DAC in one of the workshops that are taking place that day.
One workshop is on Design Automation for Beyond CMOS Technologies. Before getting to design automation, it is good to start with which technologies are potentially… Read More
Previously, I examined chip design in the late 1970s and early 1980s. It was a nostalgic ride – thanks to all those who shared their stories. I enjoyed reading all of them. I drew two basic conclusions in the prior post:
[LIST=1]
Every SoC project that I know of wants to finish on time, under budget, and maximize profits per device. When I first started out doing DRAM design I learned that we could maximize profit by doing shrinks of existing designs, move from ceramic to plastic packages, and reduce the amount of time spent on a tester. Today, the economic … Read More
How should we assess the risk of harmful metastability in a clock domain crossing (CDC) when the semiconductor process has significant parameter variability? One possibility is to determine the MTBF of a synchronizer at the worst-case corner of the CDC. But that approach has some conflicting complications:
Hybrid IP Prototyping Kit from Synopsys!
Synopsys has launched IP Accelerated initiative last year. The goal was clearly to accelerate Time-To-Market by providing a complete set of “tools” to augment design productivity:
Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.
It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot