Interview with David Tester VP of Engineering Mach42David Tester is the VP of Engineering at…Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node SurvivalThe philosophy of relying on a single, unified…Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
Will/should others follow?
TSMC vs Intel impact?
Moving Apple’s supply chain further overseas
Apples move to self served silicon was no surprise…..
It has been speculated for years and we have talked about it many times. It makes more sense for Apple to have silicon, custom designed for their applications and products… Read More
I believe I asked this question a year or two ago and answered it for the absolute bleeding edge of datacenter performance – Google TPU and the like. Those hyperscalars (Google, Amazon, Microsoft, Baidu, Alibaba, etc) who want to do on-the-fly recognition in pictures so they can tag friends in photos, do almost real-time machine… Read More
ClioSoft published a white paper recently entitled Best Practices are the Foundations of a Startup. The piece discusses the needs and challenges associated with building a scalable infrastructure to support growth.
Before I get into more details on ClioSoft’s white paper, I would offer my own experience on this topic – the need… Read More
Summary
Design Technology Co-Optimization (DTCO) analysis was pursued for library cell PPA estimates for gate-all-around (GAA) devices and new metallurgy options. The cell design and process recommendations are a bit surprising.
Introduction
During the “golden years” of silicon technology evolution that applied Dennard… Read More
SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely. They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification IP… Read More
Presto Engineering recently held a webinar discussing vision chip technology – what a vision chip is, what are the applications and how can you optimize its use. Samer Ismail, a design engineer at Presto Engineering with deep domain expertise in vision chip technology was the presenter. Samer takes you on a very informative … Read More
Summary
A novel spin-transfer torque magnetoresistive memory (STT-MRAM) IP offering provides an attractive alternative for demanding high-performance embedded applications.
Introduction
There is a strong need for embedded non-volatile memory IP across a wide range of applications, as depicted in the figure below.
The… Read More
For years, the lords of Lyft and Uber have declaimed their intention to vanquish car ownership and displace public transportation. It really was as simple and as blunt as that. For sure there would be collateral damage including rental car companies and taxi operators and millions of under-compensated drivers – but the bottom
As most of you know DVCon 2020 was our first conference to be cut short by the Pandemic. SemiWiki bloggers Bernard Murphy, Mike Gianfagna, and I were there with full schedules but at the last minute it was called off. It really was an eerie feeling, the emptiness of it all.
The rest of our EDA live events followed suit and went virtual … Read More
In this first part of a 2-part blog series, we look at defining worst case conditions, focusing specifically on device power.
With great power, comes great responsibility…
With each new technology node especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival