CTO Interview with Taylor Barton of Certus Semiconductor

Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering from Brigham Young University, where his M.S. emphasis was analog integrated circuit design. He has published in IEEE journals and conferences on topics including analog artificial neurons, low-power ADC design, and zero-crossing-based amplifiers.

What brought you to Certus Semi?

My first interaction with Certus Semi was at a university lecture series, where I was immediately drawn to the company’s commitment to creative solutions and its impressive track record of solving unusual technical problems. That culture matched my own drive to create, invent, and take on difficult designs. I wanted to be in an environment where technical creativity wasn’t just encouraged but required to solve high-stakes engineering problems.

What is the biggest challenge your customers are facing?

Modern chips across applications like AI, automotive, and high-performance computing demand increasingly high bump counts, which means a growing share of the die area must be allocated directly to I/O. Although I/O is critical to the operation, communication, and field reliability of every chip, chip-core engineers often see it as “dead space”, silicon area that consumes real estate and inflates production costs without directly adding core processing power. Our customers urgently need I/O libraries that pack extensive functionality, high signal integrity, and robust Electro Static Discharge (ESD) protection into the smallest possible physical footprint.

Why is your approach to solving this problem unique?

At Certus, each I/O library is tailored to the customer rather than served up as a generic off-the-shelf product. We analyze power buses, ESD constraints, and long-term reliability parameters to minimize area and maximize overall performance. We also work closely with the customer’s design team to learn exactly which features they need and which they don’t, allowing us to prune unnecessary circuits and increase density even further.

Additionally, our ESD structures routinely exceed industry-standard ESD requirements while occupying comparatively less area. That frees up valuable space for active I/O circuitry that traditional ESD networks would have otherwise consumed.

The result is a library that fits the customer’s required form factor, is easy to integrate because it has no extraneous controls and is highly optimized for the target application. In the past year alone, we have worked with customers in industries ranging from AI accelerators to automotive microcontrollers to create optimized I/O IP that minimized area and integrated seamlessly with the customer’s chip-core footprint, routing strategy, and pinout.

Certus has also expanded its analog IP offerings, adding several highly area-efficient products to our catalog. Recently, a customer needed to place a large array of ADCs and DACs in their chip. Leveraging our deep experience with compact mixed-signal I/O, we created an extremely compact, array-able custom ADC and DAC solution. Both exceeded the customer’s performance specification, and both came in smaller than the customer’s area target and are now both silicon proven. We’re building on that success with a follow-on ADC line, including an ultra-low-power 12-bit SAR ADC that will be about 25% smaller than the lead customer’s requirement.

What other approaches are being used to solve this problem?

Other industry leaders are packing ever-larger feature sets into their I/O libraries, creating broad “kitchen-sink” offerings. That gives users maximum flexibility across a wide range of potential applications, but it doesn’t optimize for area, and in semiconductor manufacturing, area is cost. Highly configurable libraries certainly have their place for general-purpose applications, but they leave behind unused control logic and bloated footprints. Consequently, they are rarely the best fit for high-bump-count chips with specific target applications where every square millimeter counts.

What challenges will your customers face in the near future?

Future libraries will increasingly be developed in low single-digit nanometer nodes. The ultra-deep-submicron transistors at these advanced nodes are extremely sensitive to overvoltage stress and are natively limited to low I/O voltages of around 1.2V. Yet, despite these physical limitations, our customers will still need to support legacy 1.8V and even 3.3V protocols using these 1.2V-tolerant devices without causing premature reliability degradation or breakdown.

Certus is uniquely positioned to solve this problem for our partners. We have extensive experience designing 3.3V-to-5V-tolerant I/O in 1.8V FinFET processes, and we have developed novel circuit topologies that extend the operational lifetime of I/O devices operating under high I/O voltage conditions.

How has AI changed your business strategy?

AI lets our engineers spend more time engineering and less time on literature review, document creation, and presentation prep. By leveraging intelligent tooling for routine administrative tasks and background research, our engineering team keeps its primary focus on the challenging circuit layout and design problems we tackle every day. This streamlined workflow directly translates into higher-quality products, greater technical precision, and significantly faster design turnaround for our customers.

Contact Certus Semiconductor

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