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“Ads definitely work, but we can’t tell you how or why or give you any evidence,” – Tim Hwang, research fellow, Georgetown Center for Security and Emerging Technology
Two recent episodes of the Freakonomics Radio podcast tackle the question “Does advertising actually work?” and they coincided with a presentation… Read More
Tony Pialis is a visionary entrepreneur focused on developing
technologies for next generation connectivity. In the last twenty 20 years, he has co-founded three semiconductor IP companies, all exclusively targeting connectivity IP. Tony is currently the CEO of Alphawave IP Inc, a leader in delivering multi-standard wireline… Read More
Earlier this year I wrote about Silicon Catalyst and a potent new addition to their In-Kind and Strategic Partner Programs, Arm. Fast-forward to today and there are real results to report. As I mentioned in the prior post, Silicon Catalyst provides a unique incubator environment which includes deeply discounted technology … Read More
You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:
What follows is the second part of a Q&A discussion with Chen Zhao… Read More
As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More
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Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More
The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow. The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More
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A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™. The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival