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Semiconductor Expert Forum

Podcast EP51: A Preview of the Needham Keynote at DAC

Podcast EP51: A Preview of the Needham Keynote at DAC
by Daniel Nenni on 12-03-2021 at 10:00 am
Categories: Uncategorized

Dan is joined by Charles Shi, Vice President & Research Analyst for Semiconductors & Semiconductor Equipment at Needham & Company. Charles will be doing an opening keynote next week at the Design Automation Conference. He covers EDA as well as semiconductor equipment at Needham.

Dan explores why Charles is… Read More

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CEO Interview: Da Chuang of Expedera

CEO Interview: Da Chuang of Expedera
by Daniel Nenni on 12-03-2021 at 6:00 am
Categories: AI, CEO Interviews, Expedera, IP

Da Chuang CEO Expedera

Da is co-founder and CEO of Expedera. Previously, he was cofounder and COO of Memoir Systems, an optimized memory IP startup, leading to a successful acquisition by Cisco. At Cisco, he led the Datacenter Switch ASICs for Nexus 3/9K, MDS, CSPG products. Da brings more than 25 years of ASIC experience at Cisco, Nvidia, and Abrizio.… Read More

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Low Power High Performance PCIe SerDes IP for Samsung Silicon

Low Power High Performance PCIe SerDes IP for Samsung Silicon
by Tom Simon on 12-02-2021 at 10:00 am
Categories: Analog Bits, Events, IP, Samsung Foundry

SerDes IP for PCIe

No matter how impressive the specifications are for an SoC, the power performance and area of the finished design all depend on the IP selected for the IO blocks. In particular, most SOCs designed for consumer and enterprise applications rely heavily on PCI Express. Because PCIe analog IP is critical to design success, Samsung … Read More

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Continuous Integration of RISC-V Testbenches

Continuous Integration of RISC-V Testbenches
by Daniel Nenni on 12-02-2021 at 6:00 am
Categories: AMIQ EDA, EDA

RISC V Results

In my last blog post about AMIQ EDA, I talked with CEO and co-founder Cristian Amitroaie about their support for continuous integration (CI). We discussed in some detail how their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and Verissimo SystemVerilog Linter are used in CI flows. Cristian… Read More

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Ansys to Present Multiphysics Cloud Enablement with Microsoft Azure at DAC

Ansys to Present Multiphysics Cloud Enablement with Microsoft Azure at DAC
by Daniel Nenni on 12-01-2021 at 2:00 pm
Categories: Ansys, Inc., EDA, Events

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Ansys and Microsoft  collaborated extensively over the past year to optimize and test Ansys’ signoff multiphysics simulation tools on the Azure cloud. Microsoft has invited Ansys to present the joint results in Azure’s DAC booth theater in San Francisco this year.

Two presentations are planned: covering the enablement of Ansys… Read More

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Webinar: The Backstory of PCIe 6.0 for HPC, From IP to Interconnect

Webinar: The Backstory of PCIe 6.0 for HPC, From IP to Interconnect
by Mike Gianfagna on 12-01-2021 at 8:00 am
Categories: Events, Samtec, Semiconductor Services

The Backstory of PCIe 6.0 for HPC From IP to Interconnect

PCIe, or peripheral component interconnect express, is a very popular high-speed serial computer expansion bus standard. The width and speed the standard supports essentially defines the throughput for high-performance computing (HPC) applications.  The newest version, PCIe 6.0 promises to double the bandwidth that the… Read More

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Creative Applications of Formal at Intel

Creative Applications of Formal at Intel
by Bernard Murphy on 12-01-2021 at 6:00 am
Categories: EDA, Synopsys

formal image min

One of the sessions I enjoyed at the Synopsys Verification Day 2021 was a presentation on applying formal to a couple of non-traditional problem domains. I like talks of this kind because formal can sometimes be boxed into a limited set of applications, under-exploiting the potential of the technology. Intel have built a centralized… Read More

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CEO Interview: Mo Faisal of Movellus

CEO Interview: Mo Faisal of Movellus
by Daniel Nenni on 12-01-2021 at 6:00 am
Categories: AI, CEO Interviews, Chiplet, IP, Movellus

Mo Faisal Movellus

Prior to founding Movellus, Dr. Faisal held positions at semiconductor companies such as Intel and PMC Sierra. Faisal received his B.S. from the University of Waterloo, and his M.S. and Ph.D. from the University of Michigan, and holds several patents. Dr. Faisal was named a “Top 20 Entrepreneur” by the University of Michigan Zell… Read More

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System Technology Co-Optimization (STCO)

System Technology Co-Optimization (STCO)
by Daniel Payne on 11-30-2021 at 10:00 am
Categories: Chiplet, EDA, Siemens EDA

An early package prototype

My first exposure to seeing multiple die inside of a single package in order to get greater storage was way back in 1978 at Intel, when they combined two 4K bit DRAM die in one package, creating an 8K DRAM chip, called the 2109. Even Apple used two 16K bit DRAM chips from Mostek to form a 32K bit DRAM, included in the Apple III computer, circa… Read More

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High-Performance Natural Language Processing (NLP) in Constrained Embedded Systems

High-Performance Natural Language Processing (NLP) in Constrained Embedded Systems
by Kalar Rajendiran on 11-30-2021 at 6:00 am
Categories: IP, Synopsys

Demonstrator Block Diagram

Current technology news is filled with talk of many edge applications moving processing from the cloud to the edge. One of the presentations at the recently concluded Linley Group Fall Processor Conference was about AI moving from the cloud to the edge. Rightly so, there were several sessions dedicated to discussing AI and edge… Read More